AD9460-105LVDS/PCB Analog Devices Inc, AD9460-105LVDS/PCB Datasheet

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AD9460-105LVDS/PCB

Manufacturer Part Number
AD9460-105LVDS/PCB
Description
BOARD EVAL FOR AD9460-105
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9460-105LVDS/PCB

Number Of Adc's
1
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Parallel
Inputs Per Adc
1 Differential
Input Range
*
Power (typ) @ Conditions
1.9W @ 105MSPS
Voltage Supply Source
Single
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9460-105
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
105 MSPS guaranteed sampling rate (AD9460-105)
79.4 dBFS SNR/91 dBc SFDR with 10 MHz input
78.3 dBFS SNR/ with 170 MHz input
77.8 dBFS SNR/87 dBc SFDR with 170 MHz input
77.2 dBFS SNR/84 dBc SFDR with 170 MHz input
90 dBFS two-tone SFDR with 139 MHz/140 MHz input
60 fsec rms jitter
Excellent linearity
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output data capture clock available
3.3 V and 5 V supply operation
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9460 operates up to 105 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(3.4 V p-p input, 80 MSPS)
(4.0 V p-p input, 80 MSPS)
(3.4 V p-p input, 80 MSPS)
(3.4 V p-p input, 105 MSPS)
(3.4 V p-p input, 105 MSPS)
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
16-Bit, 80 MSPS/105 MSPS ADC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9460 is available in a Pb-free, 100-lead, surface-mount,
plastic package (TQFP_EP) specified over the industrial tem-
perature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
CLK+
CLK–
VIN+
VIN–
True 16-bit linearity.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
Ease of use: on-chip reference and high input impedance,
track-and-hold with adjustable analog input range, and an
output clock simplifies data capture.
Packaged in a Pb-free, 100-lead TQFP/EP.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
AD9460
BUFFER
MANAGEMENT
AND TIMING
CLOCK
FUNCTIONAL BLOCK DIAGRAM
AGND
T/H
AVDD1 AVDD2
©2006 Analog Devices, Inc. All rights reserved.
VREF
PIPELINE
REF
ADC
SENSE REFT
Figure 1.
DRGND DRVDD
16
STAGING
OUTPUT
CMOS
LVDS
REFB
OR
32
2
2
AD9460
www.analog.com
DFS
DCS MODE
OUTPUT MODE
OR
D15 TO D0
DCO

Related parts for AD9460-105LVDS/PCB

AD9460-105LVDS/PCB Summary of contents

Page 1

... The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit optimized for performance, small size, and ease of use. The AD9460 operates up to 105 MSPS, providing a superior signal- to-noise ratio (SNR) for instrumentation, medical imaging, and radar receivers using baseband (<100 MHz) and IF frequencies. ...

Page 2

... AD9460 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 5 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 REVISION HISTORY 7/06—Revision 0: Initial Version Pin Configurations and Function Descriptions ............................8 Equivalent Circuits ...

Page 3

... CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For SFDR = AVDD1, I power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. AVDD2 AD9460BSVZ-80 Temp Min ...

Page 4

... Full 78 25° Full 78 25°C 82 25°C 94 100 Full 91 25° Full 88 25°C 97 25°C 89 Full 615 Rev Page AD9460BSVZ-105 Min Typ Max Unit 77.2 78.1 dB 76.9 75.0 76.2 dB 74.5 75.2 dB 75.2 77.4 dB 74.5 72.0 75.1 dB 71.2 73.6 dB 12.7 bits 12 ...

Page 5

... Full 1.1 1.4 1.7 Full 2 AD9460BSVZ-80 AD9460BSVZ-105 Min Typ Max Min Typ 80 105 1 12.5 9.5 5.0 3.8 5.0 3.8 3.35 3.35 2.3 3.6 4.8 2.3 3 AD9460 Unit V V μA μ kΩ pF Max Unit MSPS 1 MSPS 4.8 ns cycles ns fs, rms ...

Page 6

... AD9460 TIMING DIAGRAMS N – VIN t CLKL t CLKH CLK+ CLK– Dx DCO+ DCO– t CPD N N – 1 VIN t CLKL t CLKH CLK– CLK DCO+ DCO– – – CLOCK CYCLES Figure 2. LVDS Mode Timing Diagram CLOCK CYCLES N – – – 1 Figure 3. CMOS Timing Diagram Rev ...

Page 7

... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. THERMAL RESISTANCE Rating The heat sink of the AD9460 package must be soldered to ground. −0 −0 Airflow increases heat dissipation, effectively reducing θ ...

Page 8

... SENSE 8 VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, Exposed Heat Sink 100 PIN 1 AD9460 LVDS MODE TOP VIEW (Not to Scale Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). ...

Page 9

... Out-of-Range True Output Bit. SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance ...

Page 10

... VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, Exposed Heat Sink 10 REFT 100 PIN 1 AD9460 CMOS MODE TOP VIEW (Not to Scale Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). ...

Page 11

... Out-of-Range True Output Bit. SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance ...

Page 12

... AD9460 EQUIVALENT CIRCUITS AVDD2 VIN+ 6pF 1kΩ 3.5V X1 1kΩ AVDD2 VIN– 6pF Figure 6. Equivalent Analog Input Circuit DRVDD 1.2V LVDS_BIAS 3.74kΩ Figure 7. Equivalent LVDS_BIAS Circuit DRVDD V Dx– V Figure 8. Equivalent LVDS Digital Output Circuit T/H DRVDD K I LVDSOUT Figure 10 ...

Page 13

... OUTPUT CODE Figure 16. 105 MSPS, DNL Error vs. Output Code, 10.3 MHz –1 –2 –3 –4 0 8192 16384 24576 32768 40960 49152 57344 OUTPUT CODE Figure 17. 105 MSPS, INL Error vs. Output Code, 10.3 MHz AD9460 52.500 65536 65536 ...

Page 14

... AD9460 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 12.5 25.0 FREQUENCY (MHz) Figure 18. 80 MSPS, 64k Point Single-Tone FFT, 10.3 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 12.5 25 ...

Page 15

... ANALOG INPUT AMPLITUDE (dB) CMOS Output Mode SFDR +85°C SFDR +25°C SFDR –40°C SNR +25°C SNR –40°C SNR +85° 100 150 ANALOG INPUT FREQUENCY (MHz) 3.4 V p-p, CMOS Mode AD9460 4.1 –10 0 200 ...

Page 16

... AD9460 120 SFDR dBFS 100 SNR dBFS SFDR dBc 20 SNR dB 0 –100 –90 –80 –70 –60 –50 –40 ANALOG INPUT AMPLITUDE (dB) Figure 30. 80 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level 95 SFDR +25° SFDR –40°C SNR +25°C SNR –40° SNR +85°C ...

Page 17

... Figure 37. 105 MSPS, Two-Tone SFDR vs. Analog Input Level, 139.6 MHz, 140.6 MHz 6000 5000 4000 3000 2000 1000 0 52.500 6000 5000 4000 3000 SFDR dBc 2000 1000 0 –20 –10 0 Rev Page BIN Figure 38. 80 MSPS, Grounded Input Histogram BIN Figure 39 105 MSPS, Grounded Input Histogram AD9460 ...

Page 18

... AD9460 0.6 0.5 0.4 0.3 0.2 105MSPS 0.1 0 –0.1 80MSPS –0.2 –0.3 –0.4 –40 – TEMPERATURE (°C) Figure 40. Gain vs. Temperature 79 78 170.3MHz, 80MSPS 77 76 170.3MHz, 105MSPS 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ANALOG INPUT RANGE (V p-p) Figure 41. SNR vs. Analog Input Range ...

Page 19

... The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value MIN MAX Rev Page AD9460 ) ) PD ...

Page 20

... MODE pin. ANALOG INPUT AND REFERENCE OVERVIEW A stable and accurate 0.5 V band gap voltage reference is built into the AD9460. The input range can be adjusted by varying the reference voltage applied to the AD9460, using either the internal reference or an externally applied reference voltage. ...

Page 21

... ADCs that support single-ended analog input configurations. With the 1.7 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9460 analog input is nominally 3.4 V p-p or 1.7 V p-p on each input (VIN+ or VIN−). VIN+ 1.7V p-p VIN– ...

Page 22

... AVDD2 must be held within 5% of the specified voltage. AD9460 CLK– The DRVDD supply of the AD9460 is a dedicated supply for the digital outputs in either LVDS or CMOS output modes. When in LVDS mode, the DRVDD should be set to 3 CMOS mode, the DRVDD supply can be connected from 2 3.6 V for compatibility with the receiving logic ...

Page 23

... Pin 5 (LVDS_BIAS) to ground. Dynamic performance, including both SFDR and SNR, maximizes when using the AD9460 in LVDS mode; designers are encouraged to take advantage of this mode. The AD9460 outputs include com- plementary LVDS outputs for each data bit (Dx+/Dx−), the overrange output (OR+/OR− ...

Page 24

... Software is provided to enable the user to download the captured data via the USB port. This software also includes a behavioral model of the AD9460 and many other high speed ADCs. Behavioral modeling of the AD9460 using ADIsimADC™ software is also available at www.analog.com/ADIsimADC. The ADIsimADC software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology ...

Page 25

... D14_C D14_T D15_C D15_T DRGND DRVDD OR_C OR_T AGND AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND SFDR EPAD + Figure 50. Evaluation Board Schematic Rev Page AD9460 D0_T D0_T 50 D0_C (LSB) D0_C 49 DRVDD DRVDD 48 DRGND DRGND 47 AGND GND 46 AVDD1 VCC 45 AVDD1 VCC ...

Page 26

... AD9460 Figure 51. Evaluation Board Schematic, Encode, Optional Encode and Power Options Rev Page ...

Page 27

... C108 C109 C110 DNP DNP DNP C22 C59 C93 C96 C97 0.1µF 0.1µF DNP 0.1µF 0.1µF Rev Page AD9460 C60 C10 C61 C75 0.1µF 0.1µF DNP DNP C29 C19 DNP DNP C70 C45 C49 DNP ...

Page 28

... AD9460 Figure 53. Evaluation Board Schematic Rev Page ...

Page 29

... Table 11. AD9460 Customer Evaluation Board Bill of Materials Item Qty. Reference Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 45 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C18, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, ...

Page 30

... AD9460 Item Qty. Reference Designator C1, C44, C55 28 22 C13, C14, C16, C17, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, 1 C93, C108, C109, C110 C98 1 30 E15 R1 R5, R7 H1, H2 P21, P22 1 DNP = do not populate. All items listed in this category are not populated. ...

Page 31

... SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. ORDERING GUIDE Model Temperature Range 1 AD9460BSVZ-80 –40°C to +85°C AD9460BSVZ-105 1 –40°C to +85°C AD9460-80LVDS/PCB AD9460-105LVDS/PCB Pb-free part. 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 PIN 1 ...

Page 32

... AD9460 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06006-0-7/06(0) Rev Page ...

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