AD9461-LVDS/PCB Analog Devices Inc, AD9461-LVDS/PCB Datasheet
AD9461-LVDS/PCB
Specifications of AD9461-LVDS/PCB
Related parts for AD9461-LVDS/PCB
AD9461-LVDS/PCB Summary of contents
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... The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit optimized for performance, small size, and ease of use. The AD9461 operates up to 130 MSPS, providing a superior signal- to-noise ratio (SNR) for instrumentation, medical imaging, and radar receivers using baseband (<100 MHz) and IF frequencies. ...
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... AD9461 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 5 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 REVISION HISTORY 4/06—Revision 0: Initial Version Pin Configurations and Function Descriptions ............................8 Equivalent Circuits ...
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... Full Full 3.2 Full Full Full 3.14 Full 4.75 Full 3.0 Full 3.0 Full Full Full Full Full Full Full Full Rev Page AD9461 Typ Max Unit 16 Bits Guaranteed ±0.1 +4.2 mV ±0 FSR +3.4 % FSR ±0.6 +1.0 LSB +1.3 LSB ±5.0 +7 LSB +1 ...
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... Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full Rev Page AD9461BSVZ Min Typ Max Unit 76.3 77.7 dB 76.0 dB 74.2 76.0 dB 73.8 dB 74.4 dB 75.3 dB 74.0 76 ...
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... Full 1.1 1.4 1.7 Full 2 AD9461BSVZ Temp Min Typ Max Full 130 Full 1 Full 7.7 Full 3.1 Full 3.1 Full 3.35 Full 2.3 3.6 4.8 Full 13 Full 60 AD9461 Unit V V μA μ kΩ pF Unit MSPS MSPS Cycles fsec rms ...
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... AD9461 TIMING DIAGRAMS N – CLKL t CLKH CLK+ CLK– DATA OUT DCO+ DCO– t CPD N N – 1 VIN t CLKL t CLKH CLK– CLK DCO+ DCO– – – CLOCK CYCLES Figure 2. LVDS Mode Timing Diagram CLOCK CYCLES N – – – 1 Figure 3. CMOS Timing Diagram Rev ...
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... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. THERMAL RESISTANCE Rating The heat sink of the AD9461 package must be soldered to ground. −0 −0 Airflow increases heat dissipation, effectively reducing θ ...
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... SENSE 8 VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, Exposed Heat Sink 100 PIN 1 AD9461 LVDS MODE TOP VIEW (Not to Scale Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). ...
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... Out-of-Range True Output Bit. SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <40 MHz or >215 MHz. For applications with analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR performance ...
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... VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, Exposed Heat Sink 10 REFT 100 PIN 1 AD9461 CMOS MODE TOP VIEW (Not to Scale Figure 5. 100-Lead TQFP_EP, Pin Configuration in CMOS Mode Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). ...
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... Out-of-Range True Output Bit. SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <40 MHz or >215 MHz. For applications with analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR performance ...
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... AD9461 EQUIVALENT CIRCUITS AVDD2 VIN+ 6pF 1kΩ 3.5V X1 1kΩ AVDD2 VIN– 6pF Figure 6. Equivalent Analog Input Circuit DRVDD 1.2V LVDSBIAS 3.74kΩ Figure 7. Equivalent LVDS_BIAS Circuit DRVDD V DX– V Figure 8. Equivalent LVDS Digital Output Circuit T/H DRVDD K I LVDSOUT ...
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... ANALOG INPUT FREQUENCY (MHz) 95 SFDR = +85° SFDR = +25°C SFDR = –40°C 80 SNR = –40°C 75 SNR = +85°C SNR = +25° 100 150 ANALOG INPUT FREQUENCY (MHz) Figure 17. 130 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p, CMOS Output Mode AD9461 57344 65536 200 200 ...
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... AD9461 120 SFDR dBFS 100 SFDR dBc 80 60 SNR dBFS 40 20 SNR dB 0 –90 –80 –70 –60 –50 –40 ANALOG INPUT AMPLITUDE (dB) Figure 18. 130 MSPS,170.3 MHz SNR/SFDR vs. Analog Input Amplitude 95 SFDR = +25° SFDR = –40°C SFDR = +85° SNR = +85° 100 ANALOG INPUT FREQUENCY (MHz) Figure 19 ...
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... Figure 27. 130 MSPS, SNR/SFDR vs. Analog Input Common Mode 3.6 3.8 4.0 4.2 45 Figure 28. Single-Tone SNR/SFDR vs. Sample Rate 170.3 MHz 60 80 Rev Page AD9461 SFDR dBc SNR dB 3.1 3.3 3.5 3.7 3.9 ANALOG INPUT COMMON-MODE VOLTAGE (V) SFDR dBc SNR 105 125 145 SAMPLE RATE (MSPS) 4 ...
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... AD9461 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay ( The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. ...
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... The internal reference voltage is trimmed during the production test; therefore, there is little advantage to the user supplying an external voltage reference to the AD9461. The gain trim is performed with the AD9461 input range set to 3.4 V p-p nominal (SENSE connected to AGND). Because of this trim, and the maximum ac performance provided by the 3.4 V p-p analog input range, there is little benefit to using analog input ranges < ...
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... ADCs that support single- ended analog input configurations. With the 1.7 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9461 analog input is nominally 3.4 V p-p or 1.7 V p-p on each input (VIN+ or VIN−). VIN+ 1.7V p-p VIN– ...
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... Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9461 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in CLK+ LVDS mode, the DRVDD should be set to 3 ...
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... With OUTPUT MODE = 0 (AGND), the AD9461 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9461 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7. Duty Cycle Stabilizer The DCS circuit is controlled by the DCS MODE pin ...
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... The ADIsimADC™ software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9461 and other high speed ADCs with or without hardware evaluation boards. The user can choose to remove the translator and terminations to access the LVDS outputs directly ...
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... AD9461 XTALPWR P1 1 EXTREF P2 2 DRGND DRVDD 4 GND P1 1 VCC P2 2 GND DRVDD D11_C/D6_Y MTHOLE6 H4 D11_T/D7_Y D12_C/D8_Y MTHOLE6 D12_T/D9_Y H3 D13_C/D10_Y D13_T/D11_Y GND D14_C/D12_Y MTHOLE6 H1 D14_T/D13_Y DRGND D15_C/D14_Y MTHOLE6 D15_T/D15_Y (MSB) H2 DRGND DRVDD DOR_C DOR_T/DOR_Y GND VCC VCC VCC VCC VCC VCC ...
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... Figure 36. Evaluation Board Schematic, Encode, Optional Encode, and Power Options Rev Page AD9461 ...
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... AD9461 BYPASS CAPACITORS VCC + C64 C43 10µF 0.1µF GND VCC C11 0.1µF GND DRVDD + C65 C47 10µF 0.1µF DRGND 5V + C56 C85 10µF 0.1µF GND 5V GND 5V GND DNP = DO NOT POPULATE C35 C32 C30 C28 C27 0.1µF 0.1µF 0.01µ ...
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... Figure 38. Evaluation Board Schematic Rev Page AD9461 ...
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... AD9461 Table 11. AD9461 Customer Evaluation Board Bill of Material Item Qty. Reference Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, ...
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... DNP ECLOSC DIP4(14) DNP MTHOLE6 MTHOLE6 DNP Balun transformer SM-22 DNP Transformer ADT1-1WT DNP Term strip PTMICRO4 DNP Rev Page AD9461 1 Manufacturer Mfg. Part No. Digi-Key 478-1699-2 Corporation Digi-Key 490-1717-1-ND Corporation Mouser 517-6111TG Electronics ARFX1231-ND Digi-Key Corporation Samtec, Inc. TSW-120-08-L- D-RA ...
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... DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. ORDERING GUIDE Model Temperature Range 1 AD9461BSVZ –40°C to +85°C AD9461-LVDS/PCB Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 16.00 BSC SQ 1.20 MAX 14 ...