AD9445-IF-LVDS/PCB Analog Devices Inc, AD9445-IF-LVDS/PCB Datasheet
AD9445-IF-LVDS/PCB
Specifications of AD9445-IF-LVDS/PCB
Related parts for AD9445-IF-LVDS/PCB
AD9445-IF-LVDS/PCB Summary of contents
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... Optional features allow users to implement various selectable operating conditions, including input range, data format select, high IF sampling mode, and output data mode. The AD9445 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C. ...
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... AD9445 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 REVISION HISTORY 10/05—Revision 0: Initial Version Terminology .......................................................................................9 Pin Configurations and Function Descriptions ......................... 10 Equivalent Circuits ...
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... Full 335 364 Full 169 196 Full 63 78 Full 14 Full 1 Full 0.2 Full 2.2 2.4 Full 2.0 Rev Page AD9445 AD9445BSVZ-125 Min Typ Max Unit 14 Bits Guaranteed − ±3 mV − FSR − FSR −0.6 ±0.25 +0.65 LSB 5 ±0.8 LSB − ...
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... Rev Page AD9445BSVZ-125 Min Typ Max Unit 74.1 dB 72.9 73.8 dB 72.5 dB 72.3 73 72.9 dB 71 ...
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... TWO-TONE SFDR f = 30.3 MHz @ −7 dBFS, IN 31.3 MHz @ −7 dBFS f = 170.3 MHz @ −7 dBFS, IN 171.3 MHz @ −7 dBFS ANALOG BANDWIDTH 1 RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125 ENABLE = high (AVDD1). AD9445BSVZ-105 Temp Min Typ Max 25°C 95 25°C ...
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... Max Min Typ 2.0 0.8 200 +10 − 3.25 0.2 545 247 1.375 1.125 0.2 1.5 1.6 1.3 1.5 1.4 1.7 1.1 1 AD9445BSVZ-105 AD9445BSVZ-125 Typ Max Min Typ 125 10 8.0 3.2 3.2 3.35 3.35 3.6 4.8 2.3 3 Max Unit V 0.8 V 200 μA +10 μ ...
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... CLK+ CLK– DATA OUT DCO+ DCO– t CPD N N – 1 VIN t CLKL t CLKH CLK– CLK DCO+ DCO– – – CLOCK CYCLES Figure 2. LVDS Mode Timing Diagram CLOCK CYCLES N – – – 1 Figure 3. CMOS Timing Diagram Rev Page AD9445 ...
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... maximum rating conditions for extended periods may affect −0 device reliability. −0 −0 +0.3 V THERMAL RESISTANCE − The heat sink of the AD9445 package must be soldered to ground. − − Table 6. –0 DRVDD + 0.3 V Package Type –0 AVDD1 + 0.3 V 100-lead TQFP/EP –0 AVDD1 + 0.3 V Typical θ ...
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... The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Rev Page AD9445 ) PD ...
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... AVDD2 16 AVDD2 17 AVDD1 18 AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN– 23 AGND 24 AVDD2 25 DNC = DO NOT CONNECT 100 PIN 1 AD9445 LVDS MODE TOP VIEW (Not to Scale Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode Rev Page DRGND 74 D8+ 73 D8– 72 D7+ D7– D6+ 69 D6– DCO+ 68 DCO– ...
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... D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit. Rev Page AD9445 ...
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... Out-of-Range True Output Bit. RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog inputs > ...
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... AVDD1 18 AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN– 23 AGND 24 AVDD2 DNC = DO NOT CONNECT Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode AD9445 CMOS MODE TOP VIEW (Not to Scale) Rev Page AD9445 75 DRGND (LSB DNC 70 DNC 69 DNC DCO+ 68 DCO– 67 DNC 66 65 DNC 64 DRVDD ...
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... AD9445 Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic 1 DCS MODE 62 66 DNC 3 OUTPUT MODE 4 DFS 5 LVDS_BIAS 20 34, 36, 38, AVDD1 SENSE 8 VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, Exposed Heat Sink 10 REFT 11 REFB 31, 35, 37 AVDD2 22 VIN+ 23 VIN− ...
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... Figure 9. Equivalent CMOS Digital Output Circuit RF ENABLE, DCS MODE, OUTPUT MODE, DFS 30kΩ Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE AVDD2 3k Ω 3k Ω 2.5k Ω Figure 11. Equivalent Sample Clock Input Circuit AD9445 VDD CLK– 2.5k Ω ...
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... Figure 15. AD9445-125 64k Point Single-Tone FFT/125 MSPS/225.3 MHz 125MSPS 100.3MHz @ –1.0dBFS SNR = 0dB ENOB = 12.1BITS SFDR = 96dBc 46.875 62.500 Figure 16. AD9445-125 64k Point Single-Tone FFT/125 MSPS/300.3 MHz 125MSPS 170.3MHz @ –1.0dBFS SNR = 73.2dB ENOB = 12.0BITS SFDR = 91dBc 46.875 62.500 Figure 17. AD9445-125 64k Point Single-Tone FFT/125 MSPS/450.3 MHz Rev Page 25° ...
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... Figure 21. AD9445-125 SNR/SFDR vs. Analog Input Frequency, 105 125M SFDR dBc 100 100 0 Figure 22. AD9445 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz 120 100 –20 –10 0 –100 Figure 23. AD9445-125 SNR/SFDR vs. Analog Input Level, Rev Page AD9445 SFDR +85°C SFDR –40°C SFDR +25° ...
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... Figure 27. AD9445-105 64k Point Single-Tone FFT/105 MSPS/225.3 MHz 105MSPS 100.3MHz @ –1.0dBFS SNR = 73.5dB ENOB = 11.8BITS SFDR = 93dBc 39.375 52.500 Figure 28. AD9445-105 64k Point Single-Tone FFT/105 MSPS/300.3 MHz 39.375 52.500 Figure 29. AD9445-105 64k Point Single-Tone FFT/105 MSPS/450.3 MHz Rev Page 105MSPS –10 225.3MHz @ – ...
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... Figure 33. AD9445-105 SNR/SFDR vs. Analog Input Frequency, 100 2.7 140 160 180 Figure 34. AD9445-105 SNR/SFDR vs. Analog Input Common Mode, 120 100 –20 –10 0 –100 Figure 35. AD9445-105 SNR/SFDR vs. Analog Input Level, Rev Page AD9445 SFDR +25°C SFDR +85°C SFDR –40°C SNR – ...
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... MSPS/170.3 MHz, 171.3 MHz 125MSPS 30.3MHz @ –7.0dBFS 31.3MHz @ –7.0dBFS SFDR = 102dBFS 40.875 54.500 –30 –20 –10 0 Figure 40. AD9445-105 64k Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3 MHz 40.875 54.500 Rev Page –10 –20 SFDR dBc –30 –40 WORST IMD3 dBc –50 – ...
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... Figure 47. AD9445-105 DNL Error vs. Output Code, 105 MSPS, 10.3 MHz Rev Page SAMPLE SIZE = 65538 26294 16117 15743 3493 3350 307 – – – – OUTPUT CODE Figure 45 ...
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... OUTPUT CODE Figure 50. AD9445-105 INL Error vs. Output Code, 105 MSPS, 10.3 MHz 12288 16384 Figure 51. AD9445-125 INL Error vs. Output Code, 125 MSPS, 10.3 MHz 12288 16384 Figure 53. AD9445-125 SNR vs. Analog Input Range, 125 MSPS/170.3 MHz, Rev Page 1.0 ...
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... SFDR dBc 75 300.3MHz SFDR dBc 70 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ANALOG INPUT RANGE (V p-p) Figure 56. AD9445-125 SFDR vs. Analog Input Range, 125 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz 3.4 3.6 3.8 4.0 4.2 120 140 160 3.4 3.6 3.8 4 ...
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... Internal Reference Trim The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the AD9445. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9445. The gain trim is performed with the AD9445 input range set to 2 ...
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... With the 1 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9445 analog input is nominally 2.0 V p-p or 1.0 V p-p on each input (VIN+ or VIN−). The AD9445 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 kΩ ...
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... For that reason, considerable care was taken in the design of the clock inputs of the AD9445, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to the clock duty cycle ...
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... Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9445 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in LVDS mode, the DRVDD should be set to 3 CMOS mode, the DRVDD supply can be connected from 2 ...
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... With OUTPUT MODE = 0 (AGND), the AD9445 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9445 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7. Duty Cycle Stabilizer The DCS circuit is controlled by the DCS MODE pin ...
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... The ADIsimADC™ software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9445 and other high speed ADCs with or without hardware evaluation boards. The user can choose to remove the translator and terminations to access the LVDS outputs directly ...
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... DRVDD 89 OR_C 90 OR_T 91 AGND 92 AVDD1 93 AVDD1 94 AVDD1 95 AVDD1 96 AVDD1 97 AVDD1 98 AGND 99 AGND 100 AGND EPAD 101 + Figure 67. AD9445 Evaluation Board Schematic Rev Page D0_T D0_T 49 D0_C D0_C (LSB) 48 DRVDD DRVDD 47 DRGND DRGND 46 AGND GND 45 AVDD1 VCC 44 VCC AVDD1 43 AVDD1 VCC 42 AGND ...
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... CR1 CR2 Figure 68. AD9445 Evaluation Board Schematic (Continued) Rev Page AD9445 ...
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... C94 C95 C22 C59 C93 C96 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF Figure 69. AD9445 Evaluation Board Schematic (Continued) Rev Page C50 C60 C10 C61 C75 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF ...
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... Figure 70. AD9445 Evaluation Board Schematic (Continued) Rev Page AD9445 ...
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... AD9445 Table 11. AD9445-125 Baseband Customer Evaluation Board Bill of Materials Item Qty. Reference Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, ...
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... H1, H2 P21, P22 1 Parts not populated. Table 12. AD9445-125 IF Customer Evaluation Board Bill of Materials Item Qty. Reference Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, ...
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... AD9445 Item Qty. Reference Designator 29 23 C13, C14, C16, C17, C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, 1 C108, C109, C110 C98 1 31 E15 R1 R5, R7 H1, H2 P21, P22 1 Parts not populated. Description ...
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... SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. ORDERING GUIDE Model Temperature Range 1 AD9445BSVZ-125 –40°C to +85°C AD9445BSVZ-105 1 –40°C to +85°C AD9445-IF-LVDS/PCB AD9445-BB-LVDS/PCB Pb-free part. 16.00 BSC SQ 1.20 0.75 MAX 0.60 14.00 BSC SQ 0.45 ...
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... AD9445 NOTES Rev Page ...
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... NOTES Rev Page AD9445 ...
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... AD9445 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05489–0–10/05(0) Rev Page ...