AD9446-100LVDS/PCB Analog Devices Inc, AD9446-100LVDS/PCB Datasheet

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AD9446-100LVDS/PCB

Manufacturer Part Number
AD9446-100LVDS/PCB
Description
BOARD EVAL FOR AD9446-100 LVDS
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9446-100LVDS/PCB

Number Of Adc's
1
Number Of Bits
16
Sampling Rate (per Second)
100M
Data Interface
Parallel
Inputs Per Adc
1 Single Ended
Input Range
2 ~ 4 Vpp
Power (typ) @ Conditions
2.6W @ 100MSPS
Voltage Supply Source
Single
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9446
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
FEATURES
100 MSPS guaranteed sampling rate (AD9446-100)
83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)
82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation
APPLICATIONS
MRI receivers
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
product operates up to a 100 MSPS, providing superior SNR for
instrumentation, medical imaging, and radar receivers
employing baseband (<100 MHz) IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL = ±0.4 LSB typical
INL = ±3.0 LSB typical
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9446 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
CLK+
CLK–
VIN+
VIN–
True 16-bit linearity.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
Packaged in a Pb-free, 100-lead TQFP/EP package.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
AD9446
BUFFER
MANAGEMENT
AND TIMING
16-Bit, 80/100 MSPS ADC
CLOCK
FUNCTIONAL BLOCK DIAGRAM
AGND
T/H
AVDD1 AVDD2
© 2005 Analog Devices, Inc. All rights reserved.
VREF
PIPELINE
REF
ADC
Figure 1.
SENSE REFT
DRGND DRVDD
16
STAGING
OUTPUT
CMOS
LVDS
REFB
OR
32
2
2
AD9446
www.analog.com
OUTPUT MODE
OR
D15 TO D0
DCO
DFS
DCS MODE

Related parts for AD9446-100LVDS/PCB

AD9446-100LVDS/PCB Summary of contents

Page 1

... Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. The AD9446 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C. PRODUCT HIGHLIGHTS 1 ...

Page 2

... AD9446 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 REVISION HISTORY 10/05—Revision 0: Initial Version Terminology .......................................................................................9 Pin Configurations and Function Descriptions ......................... 10 Equivalent Circuits ...

Page 3

... Full 335 365 Full 204 234 Full 68 75 Full 14 Full 1 Full 0.2 Full 2.4 2.6 Full 2.2 Rev Page AD9446 AD9446BSVZ-100 Min Typ Max Unit 16 Bits Guaranteed −5 ±0 −3 ±0 FSR −2 ±0 FSR −0.85 ±0.4 +0.85 LSB − ...

Page 4

... Rev Page AD9446BSVZ-100 Min Typ Max Unit 78.4 79.7 dB 78.3 79.5 dB 77.9 dB 77.7 79.0 dB 77.6 dB 78.9 dB 78 ...

Page 5

... Full 325 Rev Page AD9446 AD9446BSVZ-100 Min Typ Max Unit 82 92 dBc 82 89 dBc 79 dBc 81 89 dBc 77 dBc 84 dBc 83 dBc 74 dBc 94 ...

Page 6

... Max Min Typ 2.0 0.8 200 +10 − 3.25 0.2 545 247 1.375 1.125 0.2 1.5 1.6 1.3 1.5 1.4 1.7 1.1 1 AD9446BSVZ-80 AD9446BSVZ-100 Typ Max Min Typ 100 1 10 4.0 4.0 3.35 3.35 3.6 4.8 2.3 3 Max Unit V 0.8 V 200 μA +10 μ ...

Page 7

... CLK+ CLK– DATA OUT DCO+ DCO– t CPD N N – 1 VIN t CLKL t CLKH CLK– CLK DCO+ DCO– – – CLOCK CYCLES Figure 2. LVDS Mode Timing Diagram CLOCK CYCLES N – – – 1 Figure 3. CMOS Timing Diagram Rev Page AD9446 ...

Page 8

... maximum rating conditions for extended periods may affect −0 device reliability. −0 −0 +0.3 V THERMAL RESISTANCE − The heat sink of the AD9446 package must be soldered to − ground. − –0 DRVDD + 0.3 V Table 6. –0 AVDD1 + 0.3 V Package Type –0 AVDD1 + 0.3 V 100-lead TQFP/EP – ...

Page 9

... The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Rev Page AD9446 ) PD ...

Page 10

... AVDD2 17 AVDD1 18 AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN– 23 AGND 24 AVDD2 25 DNC = DO NOT CONNECT 100 PIN 1 AD9446 LVDS MODE TOP VIEW (Not to Scale Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode Rev Page DRGND 74 D10+ 73 D10– 72 D9+ 71 D9– 70 D8+ D8– 69 DCO+ ...

Page 11

... D7 True Output Bit. Data Clock Output—Complement. Data Clock Output—True. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit. Rev Page AD9446 ...

Page 12

... AD9446 Pin No. Mnemonic 79 D12− 80 D12+ 81 D13− 82 D13+ 83 D14− 84 D14+ 85 D15− 86 D15+ (MSB) 89 OR− 90 OR+ Description D12 Complement Output Bit. D12 True Output Bit. D13 Complement Output Bit D13 True Output Bit. D14 Complement Output Bit D14 True Output Bit. ...

Page 13

... AVDD1 19 AVDD1 20 AGND 21 VIN+ 22 VIN– 23 AGND 24 AVDD2 DNC = DO NOT CONNECT Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode AD9446 CMOS MODE TOP VIEW (Not to Scale) Rev Page AD9446 75 DRGND 74 D4+ D3 D1+ 70 D0+ (LSB) 69 DNC DCO+ 68 DCO– 67 DNC 66 65 DNC ...

Page 14

... AD9446 Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic 1 DCS MODE 62 66, 69, DNC 3 OUTPUT MODE 4 DFS 5 LVDS_BIAS 20 34, 36, AVDD1 38 45 SENSE 8 VREF 9, 21, 24, 39, 42, 46, 91, 98, AGND 99, 100, Exposed Heat Sink 10 REFT 11 REFB 31, 35, 37 AVDD2 22 VIN+ 23 VIN− ...

Page 15

... DRVDD DX Figure 9. Equivalent CMOS Digital Output Circuit DCS MODE, OUTPUT MODE, DFS 30kΩ Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE AVDD2 3k Ω 3k Ω 2.5k Ω Figure 11. Equivalent Sample Clock Input Circuit AD9446 VDD CLK– 2.5k Ω ...

Page 16

... Figure 15. AD9446-100 64k Point Single-Tone FFT/100 MSPS/92.16 MHz 100MSPS 30.3MHz @ –1.0dBFS SNR = 79.5dB ENOB = 12.9BITS SFDR = 90dBc 37.5 50.0 Figure 16. AD9446-100 DNL Error vs. Output Code, 100 MSPS, 10.3 MHz 100MSPS 70.3MHz @ –1.0dBFS SNR = 79.0dB ENOB = 12.9BITS SFDR = 86dBc 37.5 50.0 Figure 17. AD9446-100 INL Error vs. Output Code, 100 MSPS, 10.3 MHz Rev Page 25° ...

Page 17

... Figure 21. AD9446-80 64k Point Single-Tone FFT/80 MSPS/100.3 MHz 0.6 0.4 0.2 0 –0.2 –0.4 –0 8192 37.5 Figure 22. AD9446-80 DNL Error vs. Output Code, 80 MSPS, 10.3 MHz –1 –2 –3 – 8192 37.5 Figure 23. AD9446-80 INL Error vs. Output Code, 80 MSPS, 10.3 MHz Rev ...

Page 18

... ANALOG INPUT AMPLITUDE (dB) Figure 26. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS 120 140 160 180 Figure 27. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS, 2.0 V p-p 120 140 160 180 Figure 28. AD9446-100 SNR vs. Input Range, 30.3 MHz, −30 dBFS –30 –20 – ...

Page 19

... SFDR (dBc) –40°C 90 SFDR (dBc) +25° SNR (dB) +85°C SNR (dB) +25° 100 ANALOG INPUT FREQUENCY (MHz) Figure 30. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 3.2 V p-p 95 SFDR (dBc) +25°C SFDR (dBc) –40°C 90 SFDR (dBc) +85° SNR (dB) +25°C 75 SNR (dB) +85° ...

Page 20

... Figure 39. AD9446-100 Two-Tone SFDR vs. Analog Input Level 100 MSPS/ –100 –120 WORST IMD3 dBFS –130 –140 –30 –20 –10 0 Figure 40. AD9446-80 64k Point Two-Tone FFT/80 MSPS/9.8 MHz, 10.8 MHz 100MSPS 69.3MHz @ –7.0dBFS 70.3MHz @ –7.0dBFS SFDR = 92dBc –100 –110 –120 –130 37.5 50 ...

Page 21

... WORST IMD3 dBFS –130 –100 –90 –80 –70 –60 –50 –40 FUNDAMENTAL LEVEL (dB) Figure 44. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/ 69.3 MHz, 70.3 MHz SAMPLE SIZE = 65538 4073 1458 426 80 22 80MSPS 69.3MHz @ –7.0dBFS 70.3MHz @ –7.0dBFS SFDR = 92dBc ...

Page 22

... Figure 49. AD9446-100 VREF vs. Temperature 450 400 350 AVDD1 300 250 200 AVDD2 150 100 DRVDD SAMPLE RATE (MSPS) Figure 50. AD9446-100 Power Supply Current vs. Sample Rate 10.3 MHz @ −1 dBFS 3.4 3.6 3.8 4.0 4 100 120 140 Rev Page 70.3MHz SFDR dBc 79 10.3MHz SFDR dBc 78 30 ...

Page 23

... SFDR dBc 95 80M SFDR dBc 90 85 80M SNR dB 80 100M SNR SAMPLE RATE (MSPS) Figure 54. AD9446 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz 80 90 100 110 Rev Page AD9446 ...

Page 24

... AD9446. The gain trim is per- formed with the AD9446 input range set to 3.2 V p-p nominal (SENSE connected to AGND). Because of this trim and the maximum ac performance provided by the 3.2 V p-p analog input range, there is little benefit to using analog input ranges < ...

Page 25

... ADCs that support single- ended analog input configurations. With the 1.6 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9446 analog input is nominally 3.2 V p-p or 1.6 V p-p on each input (VIN+ or VIN−). Resulting VREF (V) N/A ⎛ ...

Page 26

... For that reason, considerable care was taken in the design of the clock inputs of the AD9446, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to the clock duty cycle ...

Page 27

... Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9446 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in LVDS mode, the DRVDD should be set to 3 CMOS mode, the DRVDD supply can be connected from 2 ...

Page 28

... With OUTPUT MODE = 0 (AGND), the AD9446 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9446 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7. Duty Cycle Stabilizer The DCS circuit is controlled by the DCS MODE pin ...

Page 29

... The ADIsimADC™ software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9446 and other high speed ADCs with or without hardware evaluation boards. The user can choose to remove the translator and terminations to access the LVDS outputs directly ...

Page 30

... DRVDD 89 OR_C 90 OR_T 91 AGND 92 AVDD1 93 AVDD1 94 AVDD1 95 AVDD1 96 AVDD1 97 AVDD1 98 AGND 99 AGND 100 AGND EPAD 101 + Figure 61. AD9446 Evaluation Board Schematic Rev Page D0_T D0_T 49 D0_C D0_C (LSB) 48 DRVDD DRVDD 47 DRGND DRGND 46 AGND GND 45 AVDD1 VCC 44 VCC AVDD1 43 AVDD1 VCC 42 AGND ...

Page 31

... CR1 CR2 Figure 62. AD9446 Evaluation Board Schematic (Continued) Rev Page AD9446 ...

Page 32

... C94 C95 C22 C59 C93 C96 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF Figure 63. AD9446 Evaluation Board Schematic (Continued) Rev Page C50 C60 C10 C61 C75 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF ...

Page 33

... Figure 64. AD9446 Evaluation Board Schematic (Continued) Rev Page AD9446 ...

Page 34

... AD9446 Table 11. AD9446 Customer Evaluation Board Bill of Material Reference Item Qty. Designator 1 7 C4, C6, C33, C34, C87, C88, C89 2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, ...

Page 35

... Package Header EHOLE SMA SMA Header C40MS BRES402 402 BRES402 402 ECLOSC DIP4(14) MTHOLE6 MTHOLE6 Balun transformer SM-22 Term strip PTMICRO4 Rev Page Value Manufacturer Mfg. Part No. Mouser Electronics 517-6111TG Digi-Key Corporation ARFX1231-ND Samtec, Inc. TSW-120-08-L- M/A-COM ETC1-1-13 Newark Electronics AD9446 ...

Page 36

... Model Temperature Range 1 AD9446BSVZ-80 –40°C to +85°C AD9446BSVZ-100 1 –40°C to +85°C AD9446-100LVDS/PCB AD9446-80LVDS/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05490–0–10/05(0) 16.00 BSC SQ 1.20 ...

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