AD9880/PCB Analog Devices Inc, AD9880/PCB Datasheet
AD9880/PCB
Specifications of AD9880/PCB
Related parts for AD9880/PCB
AD9880/PCB Summary of contents
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FEATURES Analog/HDMI dual interface Supports high bandwidth digital content protection RGB-to-YCbCr 2-way color conversion Automated clamping level adjustment 1.8 V/3.3 V power supply 100-lead LQFP Pb-free package RGB and YCbCr output formats Analog interface 8-bit triple ADC 100 MSPS maximum ...
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AD9880 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Interface Electrical Characteristics............................... 3 Digital Interface Electrical Characteristics ............................... 4 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels ........................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Design Guide................................................................................... 12 General ...
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SPECIFICATIONS ANALOG INTERFACE ELECTRICAL CHARACTERISTICS 3 1.8 V, ADC clock = maximum. DD Table 1. Parameter Temp RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Integral Nonlinearity 25°C No Missing Codes ...
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AD9880 Parameter Temp V Supply Voltage Full DD PV Supply Voltage Full DD I Supply Current (V ) 25° Supply Current (DV ) 25°C DVDD Supply Current (V ) 25° Supply ...
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Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD DV Supply Voltage DD PV Supply Voltage DD I Supply Current (Typical Pattern Supply Current (Typical Pattern) VDD I Supply Current (Typical Pattern) DVDD I Supply Current ...
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AD9880 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VD VDD DVDD PVDD Analog Inputs Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 GND PIN 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 ...
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AD9880 Pin Type Pin No. OUTPUTS REFERENCES 57 POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL ...
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Table 5. Pin Function Descriptions Pin Description INPUTS R Analog Input for the Red Channel 0. AIN0 G Analog Input for the Green Channel 0. AIN0 B Analog Input for the Blue Channel 0. AIN0 B R Analog Input for ...
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AD9880 Pin Description PWRDN Power-Down Control/Three-State Control. The function of this pin is programmable via Register 0x26 [2:1]. FILT External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure ...
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Pin Description 1 POWER SUPPLY V (3.3 V) Analog Power Supply. D These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible. V (1.8 V – 3.3 V) Digital Output Power Supply. ...
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AD9880 DESIGN GUIDE GENERAL DESCRIPTION The AD9880 is a fully integrated solution for capturing analog RGB or YUV signals and digitizing them for display on flat panel monitors, projectors, or PDPs. In addition, the AD9880 has a digital interface for ...
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This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9880. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to ...
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AD9880 required. Note that the SOG signal is always negative polarity. For additional detail on setting the SOG threshold and other SOG-related functions, see the Sync Processing section. 47nF R AIN 47nF B AIN 47nF G AIN 1nF SOG Figure ...
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Power Management The AD9880 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: ...
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AD9880 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9880, which must be flushed ...
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Sync Slicer The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input. The sync signal is extracted in a two step process. First, ...
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AD9880 Sync Separator As part of sync processing, the sync separator’s task is to extract Vsync from the composite sync signal. It works on the idea that the Vsync signal stays active for a much longer time than the Hsync ...
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HSYNCIN FILTER WINDOW HSYNCOUT VSYNC Vsync Filter and Odd/Even Fields The Vsync filter is used to eliminate spurious Vsyncs, maintain a consistent timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output. The filter works ...
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AD9880 HDMI RECEIVER The HDMI receiver section of the AD9880 allows the reception of a digital video stream, which is backward-compatible with DVI and able to accommodate not only video of various for- mats (RGB, YCrCb 4:4:4, 4:2:2), but also ...
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A programming example and register settings for several common conversions are listed in the Color Space Converter (CSC) Common Settings. For a detailed functional description and more programming examples, please refer to the application note AN-795, AD9880 Color space Converter ...
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AD9880 DATAIN P0 HSIN DATACLK DATAOUT HSOUT DATAIN P0 HSIN DATACLK YOUT CB/CROUT HSOUT 1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT. 2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT. Table 10. Port Red Bit ...
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SERIAL REGISTER MAP The AD9880 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11. ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value 0x12 Read/Write [7] 1******* [6] *0****** [5] **1***** [4] ***0**** [3] ****1*** [2] *****0** [1] ******0* [0] *******1 0x13 Read/Write [7:0] 00000000 0x14 Read/Write [7:0] 00000000 0x15 Read [7] 0******* ...
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Hex Read/Write Default Address or Read Only Bits Value 0x17 Read [3:0] ****0000 0x18 Read [7:0] 00000000 0x19 Read/Write [7:0] 00001000 0x1A Read/Write [7:0] 00010100 0x1B Read/Write [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [1] ******1* [0] ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value [6] *1****** [5] **0***** [4] ***0**** [3] **** 1*** [2] **** *1** 0x22 Read/Write [7:0] 4 0x23 Read/Write [7:0] 32 0x24 Read/Write [7] 1******* [6] *1****** [5] **1***** [4] ***1**** ...
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Hex Read/Write Default Address or Read Only Bits Value [1] ******1* [0] *******0 0x26 Read/Write [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****1*** [2:1] *****00* [0] *******0 0x27 Read/Write [7] 1******* [6] *0****** [5] **0***** [4] ***0**** [3] ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value 0x2F Read [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [2:0] *****000 0x30 Read [6] *0****** [5] **0***** [4] ***0**** [3:0] ****0000 0x31 Read/Write [7:4] 1001**** [3:0] ****0110 0x32 Read/Write ...
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Hex Read/Write Default Address or Read Only Bits Value 0x39 Read/Write [4:0] ***00000 0x3A Read/Write [7:0] 00000000 0x3B Read/Write [4:0] ***11001 0x3C Read/Write [7:0] 11010111 0x3D Read/Write [4:0] ***11100 0x3E Read/Write [7:0] 01010100 0x3F Read/Write [4:0] ***01000 0x40 Read/Write [7:0] ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value 0x50 Read/Write [7:0] 00100000 0x56 Read/Write [7:0] 00001111 0x57 Read/Write [7] 0******* [6] *0****** [3] ****0*** [2] *****0** 0x58 Read/Write [7] [6:4] [3] [2:0] 0x59 Read/Write [6] [5] [4] [2] ...
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Hex Read/Write Default Address or Read Only Bits Value 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] Read [3:0] 0x7E Read [7:0] 0x7F Read [7:0] 0x80 Read [7:0] 0x81 Read [6:5] 4 [3:2] [1:0] 0x82 Read ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value [3:0] 0x83 Read [1:0] 0x84 Read [6:0] 0x85 Read [3:0] 0x86 Read [7:0] 0x87 Read [6:0] 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read ...
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Hex Read/Write Default Address or Read Only Bits Value 0x90 Read [7:0] 0x91 Read [7:4] [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 7 0x95 Read [6:3] 0x96 Read [7:0] 0x97 Read [6:0] 0x98 Read [7:0] 0x99 ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value 0x9A Read [7:0] 0x9B Read [7:0] 0x9C Read [7:0] 0x9D Read [7:0] 0x9E Read [7:0] 0x9F Read [6:0] 0xA0 Read [7:0] 0xA1 Read [7:0] 0xA2 Read [7:0] 0xA3 Read [7:0] ...
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Hex Read/Write Default Address or Read Only Bits Value 0xBD Read [1:0] 0xBE Read [7:0] 0xBF Read [6:0] 0xC0 Read [7:0] 0xC1 Read [7:0] 0xC2 Read [7:0] 0xC3 Read [7:0] 0xC4 Read [7:0] 0xC5 Rea [7:0] 0xC6 Read [7:0] 0xC7 ...
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AD9880 Hex Read/Write Default Address or Read Only Bits Value 0xE0 Read [7:0] 0xE1 Read [7:0] 0xE2 Read [7:0] 0xE3 Read [7:0] 0xE4 Read [7:0] 0xE5 Read [7:0] 0xE6 Read [7:0] 0xE7 Read [6:0] 0xE8 Read [7:0] 0xE9 Read [7:0] ...
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SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 0x00 7-0 Chip Revision An 8-bit value that reflects the current chip revision. PLL DIVIDER CONTROL 0x01 7-0 PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio ...
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AD9880 0x04 7-3 Phase Adjust These bits provide a phase adjustment for the DLL to generate the ADC clock. A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift ...
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Blue Channel Offset These eight bits are the blue channel offset control. The offset control shifts the analog input, resulting in a change in brightness. Note that the function of the offset register depends on whether clamp feedback ...
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AD9880 0x13 7-0 Precoast This register allows the internally generated Coast signal to be applied prior to the Vsync signal. This is necessary in cases where pre-equalization pulses are present. The step size for this control is one Hsync period. ...
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Coast Detection Bit This bit detects activity on the EXTCLK/EXTCOAST pin. It indicates that one of the two signals is active, but it doesn’t indicate EXTCLK or EXTCOAST signal is not detected. Table ...
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AD9880 0x1B 5 Blue Clamp Select This bit selects whether the blue channel is clamped to ground or midscale. Ground clamping is used for blue in RGB applications and midscale clamping is used in YPrPb (YUV) applications. Table 30. Blue ...
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Sync Filter Window Width This 8-bit register sets the distance in 40 MHz clock periods (25 ns), which is the allowed distance for Hsync pulses before and after the expected Hsync edge. This is the heart of the ...
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AD9880 0x23 7-0 Hsync Duration An 8 bit register that sets the duration of the Hsync output pulse. The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9880 then counts a ...
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Table 48. Output Clock Select Select Result 00 ½× pixel clock 01 1× pixel clock 10 2× pixel clock 11 90° phase 1× pixel clock 0x25 5-4 Output Drive Strength These two bits select the drive strength for all the ...
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AD9880 Table 56. SOGOUT Three-State Select Result 0 Normal I2S output 1 I2S pins in high impedance mode. 0x26 3 Power-Down Polarity This bit defines the polarity of the input power-down pin. The power-up default setting is 1. Table 57. ...
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Hsync Delay MSBs Along with the eight bits following these ten bits set the delay (in pixels) from the Hsync leading edge to the start of active video. The power-up default setting is 0x104. 0x29 7-0 Hsync Delay ...
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AD9880 Table 71. DVI Hsync Polarity Detect Detect Result 0 DVI Hsync polarity is low active 1 DVI Hsync polarity is high active 0x30 4 DVI Vsync Polarity This read-only bit indicates the polarity of the DVI Vsync. Table 72. ...
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COLOR SPACE CONVERSION The default power up values for the color space con- verter coefficients (R0x35 through R0x4C) are set for ATSC RGB to YCbCr conversion. They are completely programmable for other conversions. 0x34 1 Color space Converter Enable This ...
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AD9880 Table 76. PLL_N [2:0] MCLK Divide Value 0x58 3 N_CTS_Disable This bit makes it possible to prevent the N/CTS packet on the link ...
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Table 80. Y Video Data 00 RGB 01 YCbCr 4:2:2 10 YCbCr 4:4:4 0x81 4 Active Format Information Present data 1 = active format information valid 0x81 3-2 Bar Information Table 81. B Bar Type 00 No ...
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AD9880 0x8D 7-0 Active Pixel End LSB Combined with the MSB in Register 0x8E these bits indicate the last active video pixel in the display. All pixels past this comprise a right vertical bar. If the 2-byte value is greater ...
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Table 91. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...
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AD9880 0xA0 7-0 VN7 0xA1 7-0 VN8 0xA2 7-0 Product Description Character 1 (PD1) This is the first character of 16 which contains the model number and a short description of the product. The data characters are 7-bit ASCII code. ...
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Table 96. ISRC1 Valid Description 0 ISRC1 status bits and PBs not valid 1 ISRC1 status bits and PBs valid 0xC8 2-0 ISRC Status These bits define where in the ISRC track the samples are: at least two transmissions of ...
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AD9880 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided in the AD9880 two AD9880 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface ...
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SDA t BUFF t DHO t STAH SCL Serial Interface Read/Write Examples Write to one control register: • Start signal • Slave address byte (R/W\ bit = low) • Base address byte • Data byte to base address • Stop ...
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AD9880 PCB LAYOUT RECOMMENDATIONS The AD9880 is a high-precision, high-speed analog device. To achieve the maximum performance from the part impor- tant to have a well laid-out board. The following is a guide for designing a board using ...
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Outputs (Both Data and Clocks) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which require more current that causes more internal digital noise. Shorter traces reduce the possibility of reflections. ...
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AD9880 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 98. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9880) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E ...
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Table 102. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 Value ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speeds (MHz) Model Analog 1 AD9880KSTZ-100 100 1 AD9880KSTZ-150 150 AD9880/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 0.20 0.09 7° 3.5° 25 0° 26 0.08 MAX COPLANARITY ...
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NOTES Rev Page AD9880 ...
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AD9880 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05087–0–8/05(0) Rev Page ...