AD9380/PCB Analog Devices Inc, AD9380/PCB Datasheet

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AD9380/PCB

Manufacturer Part Number
AD9380/PCB
Description
BOARD EVALUATION FOR AD9380
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9380/PCB

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Analog interface
Digital video interface
Digital audio interface
APPLICATIONS
Advanced TVs
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
2
S audio output (up to 8 channels)
R/G/B OR YPbPr
R/G/B OR YPbPr
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
DDCSDA
DDCSCL
SOGIN 0
SOGIN 1
COAST
RTERM
CKEXT
CKINV
RxC+
RxC–
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
FILT
SDA
SCL
IN0
IN1
FUNCTIONAL BLOCK DIAGRAM
DIGITAL INTERFACE
ANALOG INTERFACE
MUX
MUX
Dual-Display Interface
MUX
MUX
2:1
2:1
2:1
2:1
POWER MANAGEMENT
HDMI RECEIVER
SERIAL REGISTER
HDCP
© 2005 Analog Devices, Inc. All rights reserved.
CLAMP
PROCESSING
GENERATION
AND
CLOCK
SYNC
AND
Figure 1.
A/D
REFOUT
HDCP KEYS
REFIN
2
4
Analog/HDMI
R/G/B 8 × 3
OR YCbCr
DATACK
DE
HSYNC
VSYNC
2
R/G/B 8 × 3
OR YCbCr
HSOUT
DATACK
VSOUT
SOGOUT
REF
www.analog.com
AD9380
AD9380
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
S/PDIF
8-CHANNEL
I
MCLK
LRCLK
SCLK
2
S
DATACK
HSOUT
VSOUT
SOGOUT
DE

Related parts for AD9380/PCB

AD9380/PCB Summary of contents

Page 1

FEATURES Internal key storage for HDCP Analog/HDMI dual interface Supports high bandwidth digital content protection RGB-to-YCbCr 2-way color conversion Automated clamping level adjustment 1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats Analog interface 8-bit triple ...

Page 2

AD9380 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Analog Interface Electrical Characteristics............................... 3 Digital Interface Electrical Characteristics ............................... 4 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels ........................................................... ...

Page 3

SPECIFICATIONS ANALOG INTERFACE ELECTRICAL CHARACTERISTICS 3 1.8 V, ADC clock = maximum Table 1. Parameter Temp RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Integral Nonlinearity 25°C No Missing ...

Page 4

AD9380 Parameter Temp POWER SUPPLY V Supply Voltage Full D DV Supply Voltage Full DD V Supply Voltage Full DD PV Supply Voltage Full DD I Supply Current (V ) 25° Supply Current (DV ) 25°C DVDD ...

Page 5

Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD DV Supply Voltage DD PV Supply Voltage DD I Supply Current (Typical Pattern Supply Current (Typical Pattern) VDD I Supply Current (Typical Pattern) DVDD I Supply Current ...

Page 6

AD9380 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 PIN 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 ...

Page 8

AD9380 Pin Type Pin No. OUTPUTS REFERENCES 57 POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL ...

Page 9

Table 6. Pin Function Descriptions Mnemonic Description INPUTS R Analog Input for the Red Channel 0. AIN0 G Analog Input for the Green Channel 0. AIN0 B Analog Input for the Blue Channel 0. AIN0 B R Analog Input for ...

Page 10

AD9380 Mnemonic Description EXTCLK/COAST External Clock. This allows the insertion of an external clock source rather than the internally generated PLL-locked clock. This pin is shared with the coast function, which does not affect EXTCLK functionality. PWRDN Power-Down Control/Three-State Control. ...

Page 11

Mnemonic Description 1 POWER SUPPLY V (3.3 V) Analog Power Supply. D These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible 3.3 V) Digital Output Power Supply. ...

Page 12

AD9380 DESIGN GUIDE GENERAL DESCRIPTION The AD9380 is a fully integrated solution for capturing analog RGB or YUV signals and digitizing them for display on flat panel monitors, projectors, or plasma display panels (PDPs). In addition, the AD9380 has a ...

Page 13

The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced which results in the ADCs producing a black output (Code 0x00) when ...

Page 14

AD9380 For more detail on setting the SOG threshold and other SOG- related functions, see the Sync Processing section. 47nF R AIN 47nF B AIN 47nF G AIN 1nF SOG Figure 4. Typical Clamp Configuration for RGB/YUV Applications Clock Generation ...

Page 15

Power Management The AD9380 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: ...

Page 16

AD9380 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9380, which must be flushed ...

Page 17

Sync Processing The inputs of the AD9380 sync processing section are combinations of digital HSYNCs and VSYNCs, analog sync-on- green signal, sync-on-Y signal, and an optional external coast signal. From these signals, the AD9380 generates a precise, jitter-free (9% or ...

Page 18

AD9380 Sync Slicer The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input. The sync signal is extracted in a two-step process. First, ...

Page 19

HSYNC Filter and Regenerator The HSYNC filter is used to eliminate any extraneous pulses from the HSYNC or SOGIN inputs, outputting a clean, low jitter signal that is appropriate for mode detection and clock generation. The HSYNC regenerator is used ...

Page 20

AD9380 VSYNC Filter and Odd/Even Fields The VSYNC filter is used to eliminate spurious VSYNCs, maintain a consistent timing relationship between the VSYNC and HSYNC output signals, and generate the odd/even field output. The filter works by examining the placement ...

Page 21

Color Space Conversion (CSC) Matrix The CSC matrix in the AD9380 consists of three identical processing channels. In each channel, three input values are multiplied by three separate coefficients. Also included are an offset value for each row of the ...

Page 22

AD9380 This information is the fundamental difference between DVI and HDMI transmissions and is located in read-only registers R0x5A to R0xEE. In addition to this information, registers are provided to indicate that new information has been received. Registers with addresses ...

Page 23

SERIAL REGISTER MAP The AD9380 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. ...

Page 24

AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x12 Read/Write [7] 1******* [6] *0****** [5] **1***** [4] ***0**** [3] ****1*** [2] *****0** [1] ******0* [0] *******1 0x13 Read/Write [7:0] 00000000 0x14 Read/Write [7:0] 00000000 0x15 Read [7] 0******* [6] ...

Page 25

Hex Read/Write Default Address or Read-Only Bits Value 0x17 Read [3:0] ****0000 0x18 Read [7:0] 00000000 0x19 Read/Write [7:0] 00001000 0x1A Read/Write [7:0] 00010100 0x1B Read/Write [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [1] ******1* [0] *******0 ...

Page 26

AD9380 Hex Read/Write Default Address or Read-Only Bits Value [6] *1****** [5] **0***** [4] ***0**** [3] **** 1*** [2] **** *1** 0x22 Read/Write [7:0] 4 0x23 Read/Write [7:0] 32 0x24 Read/Write [7] 1******* [6] *1****** [5] **1***** [4] ***1**** [3] ...

Page 27

Hex Read/Write Default Address or Read-Only Bits Value [1] ******1* [0] *******0 0x26 Read/Write [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****1*** [2:1] *****00* [0] *******0 0x27 Read/Write [7] 1******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** ...

Page 28

AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x2F Read [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [2:0] *****000 0x30 Read [6] *0****** [5] **0***** [4] ***0**** [3:0] ****0000 0x31 Read/Write [7:4] 1001**** [3:0] ****0110 0x32 Read/Write [7] ...

Page 29

Hex Read/Write Default Address or Read-Only Bits Value 0x39 Read/Write [4:0] ***00000 0x3A Read/Write [7:0] 00000000 0x3B Read/Write [4:0] ***11001 0x3C Read/Write [7:0] 11010111 0x3D Read/Write [4:0] ***11100 0x3E Read/Write [7:0] 01010100 0x3F Read/Write [4:0] ***01000 0x40 Read/Write [7:0] 00000000 ...

Page 30

AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x56 Read/Write [7:0] 00001111 0x57 Read/Write [7] 0******* [6] *0****** [3] ****0*** [2] *****0** 0x58 Read/Write [7] [6:4] [3] [2:0] 0x59 Read/Write [6] [5] [4] [2] [1] [0] 0x5A Read [6:0] ...

Page 31

Hex Read/Write Default Address or Read-Only Bits Value 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] Read [3:0] 0x7E Read [7:0] 0x7F Read [7:0] 0x80 Read [7:0] 0x81 Read [6:5] 4 [3:2] [1:0] 0x82 Read [7:6] ...

Page 32

AD9380 Hex Read/Write Default Address or Read-Only Bits Value [3:0] 0x83 Read [1:0] 0x84 Read [6:0] 0x85 Read [3:0] 0x86 Read [7:0] 0x87 Read [6:0] 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read [7:0] ...

Page 33

Hex Read/Write Default Address or Read-Only Bits Value [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 0x95 7 Read [6:3] 0x96 Read [7:0] 0x97 Read [6:0] 0x98 Read [7:0] 0x99 Read [7:0] 0x9A Read [7:0] 0x9B Read ...

Page 34

AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x9E Read [7:0] 0x9F Read [6:0] 0xA0 Read [7:0] 0xA1 Read [7:0] 0xA2 Read [7:0] 0xA3 Read [7:0] 0xA4 Read [7:0] 0xA5 Read [7:0] 0xA6 Read [7:0] 0xA7 Read [7:0] 0xA8 ...

Page 35

Hex Read/Write Default Address or Read-Only Bits Value 0xBE Read [7:0] 0xBF Read [6:0] 0xC0 Read [7:0] 0xC1 Read [7:0] 0xC2 Read [7:0] 0xC3 Read [7:0] 0xC4 Read [7:0] 0xC5 Rea [7:0] 0xC6 Read [7:0] 0xC7 Read [6:0] 0xC8 7 ...

Page 36

AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0xE5 Read [7:0] 0xE6 Read [7:0] 0xE7 Read [6:0] 0xE8 Read [7:0] 0xE9 Read [7:0] 0xEA Read [7:0] 0xEB Read [7:0] 0xEC Read [7:0] 0xED Read [7:0] 0xEE Read [7:0] Register ...

Page 37

SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit value that reflects the current chip revision. PLL DIVIDER CONTROL 0x01—Bits[7:0] PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio PLLDIV. The ...

Page 38

AD9380 0x04—Bits[7:3] Phase Adjust These bits provide a phase adjustment for the DLL to generate the ADC clock. A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in ...

Page 39

SYNC 0x0E—Bits[7:0] Sync Separator Selects the maximum HSYNC pulse width for composite sync separation. Power-down default is 0x20. 0x0F—Bits[7:2] SOG Comparator Threshold Enter The enter level for the SOG slicer. Must be < exit level (Register 0x10). The power-up default ...

Page 40

AD9380 0x15—Bit[6] HSYNC 1 Detection Bit This bit is used to indicate when activity is detected on the HSYNC 1 input pin. If HSYNC is held high or low, activity is not detected. The sync processing block diagram shows where ...

Page 41

Clamp During Coast This bit permits clamping to be disabled during coast because video signals are generally not at a known back porch or midscale position during coast clamping during coast is disabled clamping during ...

Page 42

AD9380 the HSYNC leading edge. If the VSYNC leading edge occurs in Quadrant 2 or Quadrant 3, the field is set to 1 and the output VSYNC leading edge is placed in the center of the line. In this way, ...

Page 43

Output Drive Strength These two bits select the drive strength for all the high speed digital outputs (except VSOUT, A0, and O/E field). Higher drive strength results in faster rise/fall times and in general makes it easier to capture ...

Page 44

AD9380 0x27—Bit[7] Auto Power-Down Enable This bit enables the chip to go into low power mode, or seek mode if no sync inputs are detected auto power-down disabled chip powers down if no sync inputs present. ...

Page 45

HDMI Content Encrypted This read-only bit is high when HDCP decryption is in use (content is protected). The signal goes low when HDCP is not being used. Customers can use this bit to determine whether to allow copying of ...

Page 46

AD9380 COLOR SPACE CONVERSION The default power up values for the color space converter coefficients (R0x35 through R0x4C) are set for ATSC RGB to YCbCr conversion. They are completely programmable for other conversions. 0x34—Bit[1] Color Space Converter Enable This bit ...

Page 47

MCLK PLL_N These bits control the division of the MCLK out of the PLL. Table 24. PLL_N [2:0] MCLK Divide Value 0x58—Bit[3] N_CTS_Disable ...

Page 48

AD9380 0x81—Bits[6:5] Y [1:0] This register indicates whether data is RGB, 4:4:4, or 4:2:2. Table 28. Y Video Data 00 RGB 01 YCbCr 4:2:2 10 YCbCr 4:4:4 0x81—Bits[4] Active Format Information Present data active format ...

Page 49

Active Pixel End MSB See Register 0x8D. 0x8F—Bits[6:0] NDF See Register 0x87. 0x90—Bits[7:0] Audio Infoframe Version 0x91—Bits[7:4] Audio Coding Type These bits identify the audio coding so that the receiver may process audio properly. Table 36. CT [3:0] Audio ...

Page 50

AD9380 Table 39. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...

Page 51

PD2 0xA4—Bits[7:0] PD3 0xA5—Bits[7:0] PD4 0xA6—Bits[7:0] PD5 0xA7—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xA8—Bits[7:0] PD6 0xA9—Bits[7:0] PD7 0xAA—Bits[7:0] PD8 0xAB—Bits[7:0] PD9 0xAC—Bits[7:0] PD10 0xAD—Bits[7:0] PD11 0xAE—Bits[7:0] PD12 0xAF—Bits[6:0] New Data Flags See Register 0x87 for ...

Page 52

AD9380 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3—Bits[7:0] ISRC1_PB9 0xD4—Bits[7:0] ISRC1_PB10 0xD5—Bits[7:0] ISRC1_PB11 0xD6—Bits[7:0] ...

Page 53

SERIAL CONTROL PORT A 2-wire serial interface control interface is provided in the AD9380 two AD9380 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface comprises ...

Page 54

AD9380 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control ...

Page 55

PCB LAYOUT RECOMMENDATIONS The AD9380 is a high precision, high speed analog device. To achieve the maximum performance from the part important to have a well laid-out board. The following is a guide for designing a board using ...

Page 56

AD9380 OUTPUTS (BOTH DATA AND CLOCKS) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which require more current that causes more internal digital noise. Shorter traces reduce the possibility of ...

Page 57

COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 44. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9380) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E Value ...

Page 58

AD9380 Table 48. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 ...

Page 59

... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speed (MHz) Model Analog Digital 1 AD9380KSTZ-100 100 100 1 AD9380KSTZ-150 150 150 AD9380/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 25 0° ...

Page 60

NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05688–0–10/05(0) Rev Page ...

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