AD9381/PCB Analog Devices Inc, AD9381/PCB Datasheet
AD9381/PCB
Specifications of AD9381/PCB
Related parts for AD9381/PCB
AD9381/PCB Summary of contents
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FEATURES Internal HDCP keys HDMI interface Supports high bandwidth digital content protection RGB to YCbCr 2-way color conversion 1.8 V/3.3 V power supply 100-lead Pb-free LQFP RGB and YCbCr output formats Digital video interface HDMI 1.1, DVI 1.0 150 MHz ...
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AD9381 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Digital Interface Electrical Characteristics ............................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD ...
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SPECIFICATIONS ELECTRICAL CHARACTERISTICS 3 1.8 V, ADC clock = maximum Table 1. Parameter Temp DIGITAL INPUTS (5 V Tolerant) Input Voltage, High (V ) Full IH Input ...
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AD9381 Parameter I Supply Current (Typical DVDD 1, 4 Pattern) I Supply Current (Typical PVDD 1 Pattern) Power-Down Supply Current ( SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (T ) DPS Channel to Channel Differential Input ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. ...
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AD9381 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 12 ...
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Pin Type Pin No. REFERENCES 57 POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL 83 82 HDCP AUDIO DATA OUTPUTS ...
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AD9381 Mnemonic Description OUTPUTS HSOUT Horizontal Sync Output. A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data, data ...
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DESIGN GUIDE GENERAL DESCRIPTION The AD9381 is a fully integrated solution for receiving DVI/ HDMI signals and is capable of decoding HDCP-encrypted signals through connections to an internal EEPROM. The circuit is ideal for providing an interface for HDTV monitors ...
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AD9381 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. Figure 3 shows the timing operation of the AD9381. t PER ...
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TO 4:2:2 FILTER The AD9381 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color Space ...
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AD9381 AUDIO PLL SETUP Data contained in the audio infoframes, among other registers, define for the AD9381 HDMI receiver not only the type of audio, but the sampling frequency (f ). The audio infoframe also S contains information about the ...
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AUDIO BOARD LEVEL MUTING The audio can be muted through the infoframes or locally via the serial bus registers. This can be controlled with Register R0x57, Bits [7:4]. AVI Infoframes The HDMI TMDS transmission contains Infoframes with specific information for ...
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AD9381 2-WIRE SERIAL REGISTER MAP The AD9381 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table ...
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Hex Read/Write Address or Read Only Bits [4] [0] 0x25 Read/Write [7:6] [5:4] [3:2] [1] [0] 0x26 Read/Write [7] [5] [4] [3] [2:1] [0] 0x27 Read/Write [7] [6] [5] [4] [3] Default Value Register Name ***1**** Field Output Polarity *******0 ...
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AD9381 Hex Read/Write Address or Read Only Bits [2:0] 0x28 Read/Write [7:2] [1:0] 0x29 Read/Write [7:0] 0x2A Read/Write [3:0] 0x2B Read/Write [7:0] 0x2C Read/Write [3:0] 0x2D Read/Write [7:0] 0x2E Read/Write [7] [6:5] [4:0] 0x2F Read [6] [5] [4] [3] [2:0] ...
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Hex Read/Write Address or Read Only Bits [4] [3] [2] [1] 0x35 Read/Write [6:5] [4:0] 0x36 Read/Write [7:0] 0x37 Read/Write [4:0] 0x38 Read/Write [7:0] 0x39 Read/Write [4:0] 0x3A Read/Write [7:0] 0x3B Read/Write [4:0] 0x3C Read/Write [7:0] 0x3D Read/Write [4:0] 0x3E ...
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AD9381 Hex Read/Write Address or Read Only Bits 0x43 Read/Write [4:0] 0x44 Read/Write [7:0] 0x45 Read/Write [4:0] 0x46 Read/Write [7:0] 0x47 Read/Write [4:0] 0x48 Read/Write [7:0] 0x49 Read/Write [4:0] 0x4A Read/Write [7:0] 0x4B Read/Write [4:0] 0x4C Read/Write [7:0] 0x50 Read/Write ...
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Hex Read/Write Address or Read Only Bits 0x5A Read [6:0] 0x5B Read [3] 0x5E Read [7:6] [5: 0x5F Read [7:0] 0x60 Read [7:4] [3:0] 0x61 Read [5:4] [3:0] Default Value Register Name Packet Detected HDMI Mode Channel ...
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AD9381 Hex Read/Write Address or Read Only Bits 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] Read [3:0] 0x7E Read [7:0] 0x7F Read [7:0] 0x80 Read [7:0] 0x81 Read [6:5] 4 [3:2] [1:0] 0x82 Read [7:6] ...
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Hex Read/Write Address or Read Only Bits [3:0] 0x83 Read [1:0] 0x84 Read [6:0] 0x85 Read [3:0] 0x86 Read [7:0] 0x87 Read [6:0] 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read [7:0] 0x8D Read ...
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AD9381 Hex Read/Write Address or Read Only Bits 0x90 Read [7:0] 0x91 Read [7:4] [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 0x95 Read 7 [6:3] 0x96 Read [7:0] 0x97 Read [6:0] Default Value Register Name Audio ...
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Hex Read/Write Address or Read Only Bits 0x98 Read [7:0] 0x99 Read [7:0] 0x9A Read [7:0] 0x9B Read [7:0] 0x9C Read [7:0] 0x9D Read [7:0] 0x9E Read [7:0] 0x9F Read [6:0] 0xA0 Read [7:0] 0xA1 Read [7:0] 0xA2 Read [7:0] ...
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AD9381 Hex Read/Write Address or Read Only Bits 0xB8 Read [7:0] 0xB9 Read [7:0] 0xBA Read [7:0] 0xBB Read [7:0] 0xBC Read [7:0] 4 0xBD Read [1:0] 0xBE Read [7:0] 0xBF Read [6:0] 0xC0 Read [7:0] 0xC1 Read [7:0] 0xC2 ...
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Hex Read/Write Address or Read Only Bits 0xD2 Read [7:0] 0xD3 Read [7:0] 0xD4 Read [7:0] 0xD5 Read [7:0] 0xD6 Read [7:0] 0xD7 Read [6:0] 0xD8 Read [7:0] 0xD9 Read [7:0] 0xDA Read [7:0] 0xDB Read [7:0] 0xDC Read [7:0] ...
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AD9381 2-WIRE SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit value that reflects the current chip revision. 0x11—Bit[7] HSYNC Source 0 = HSYNC SOG. The power-up default is 0. These selections are ignored if Register ...
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VSYNC Duration This is used to set the output duration of the VSYNC, and is designed to be used with the VSYNC filter. This is valid only if Register 0x21, Bit 4 is set to 1. Power-up default is ...
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AD9381 0x26—Bit[7] Output Three-State When enabled, this bit puts all outputs (except SOGOUT high impedance state normal outputs all outputs (except SOGOUT) in high impedance mode. The power-up default setting is 0. 0x26—Bit[5] S/PDIF ...
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Ctrl Enable When set, this bit allows Ctrl [3:0] signals decoded from the 2 DVI to be output on the I S data pins lines Ctrl [3:0] output lines. The ...
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AD9381 0x33—Bit[7] Macrovision Detect Mode 0 = standard definition progressive scan mode. 0x33—Bit[6] Macrovision Settings Override This defines whether preset values are used for the MV line counts and pulse widths or the values stored ...
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CSC B2 LSBs 0x41—Bits[4-0] CSC B3 MSBs The default value for the 13-bit B3 is 0x1E89. 0x42—Bits[7:0] CSC B3 LSBs 0x43—Bits[4-0] CSC B4 MSBs The default value for the 13-bit B4 is 0x0291. 0x44—Bits[7:0] CSC B4 LSBs 0x45—Bits[4-0] CSC ...
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AD9381 0x5E—Bits[7:6] Channel Status Mode 0x5E—Bits[5:3] PCM Audio Data 0x5E—Bit[2] Copyright Information 0x5E—Bit[1] Linear PCM Identification 0x5E—Bit[0] Use of Channel Status Block 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number 0x60—Bits[3:0] Source Number 0x61—Bits[5:4] Clock Accuracy 0x61—Bits[3:0] Sampling Frequency Table ...
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New Data Flags (NDF) This register indicates whether data in specific sections has changed. In the address space from 0x80 to 0xFF, each register address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF NDF register. They ...
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AD9381 Table 33. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...
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PD2 0xA4—Bits[7:0] PD3 0xA5—Bits[7:0] PD4 0xA6—Bits[7:0] PD5 0xA7—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xA8—Bits[7:0] PD6 0xA9—Bits[7:0] PD7 0xAA—Bits[7:0] PD8 0xAB—Bits[7:0] PD9 0xAC—Bits[7:0] PD10 0xAD—Bits[7:0] PD11 0xAE—Bits[7:0] PD12 0xAF—Bits[6:0] New Data Flags See Register 0x87 for ...
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AD9381 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3—Bits[7:0] ISRC1_PB9 0xD4—Bits[7:0] ISRC1_PB10 0xD5—Bits[7:0] ISRC1_PB11 0xD6—Bits[7:0] ...
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SERIAL CONTROL PORT A 2-wire serial interface control is provided in the AD9381 two AD9381 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface comprises a ...
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AD9381 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control ...
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PCB LAYOUT RECOMMENDATIONS The AD9381 is a high precision, high speed digital device. To achieve the maximum performance from the part impor- tant to have a well laid-out board. The following is a guide for designing a board ...
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AD9381 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9381) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E ...
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Table 42. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 Value ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speed (MHz) Model Analog Digital 1 AD9381KSTZ-100 100 100 1 AD9381KSTZ-150 150 150 AD9381/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 25 0° ...
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NOTES Rev Page AD9381 ...
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AD9381 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05689-0-10/05(0) Rev Page ...