AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9517-4/PCBZ
• Description: BOARD EVALUATION AD9517-4
• Manufacturer: Analog Devices Inc

Specifications of AD9517-4/PCBZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs,
and tells the CP to pump up or pump down to charge or
discharge the integrating node (part of the loop filter). The
integrated and filtered CP current is transformed into a voltage
that drives the tuning node of the internal VCO through the LF
pin (or the tuning pin of an external VCO) to move the VCO
frequency up or down. The CP can be set (Register 0x010[6:4])
for high impedance (allows holdover operation), for normal
operation (attempts to lock the PLL loop), for pump up, or for
pump down (test modes). The CP current is programmable in
eight steps from (nominally) 600 μA to 4.8 mA. The exact value
of the CP current LSB is set by the CP_RSET resistor, which is
nominally 5.1 kΩ. If the value of the CP_RSET is doubled, the
resulting charge pump current range becomes 300 μA to 2.4 mA.
On-Chip VCO
The AD9517 includes an on-chip VCO covering the frequency
range shown in Table 2. Achieving low VCO phase noise was a
priority in the design of the VCO.
To tune over the wide range of frequencies covered by this VCO,
ranges are used. This is largely transparent to the user but is the
reason that the VCO must be calibrated when the PLL loop is
first set up. The calibration procedure ensures that the VCO
operating voltage is centered for the desired VCO frequency. See
the VCO Calibration section for additional information.
The on-chip VCO is powered by an on-chip, low dropout
(LDO), linear voltage regulator. The LDO provides some
isolation of the VCO from variations in the power supply
voltage level. The BYPASS pin should be connected to ground
by a 220 nF capacitor to ensure stability. This LDO employs the
same technology used in the anyCAP® line of regulators from
Analog Devices, Inc., making it insensitive to the type of
capacitor used. Driving an external load from the BYPASS pin
is not supported.
Note that the reference input signal must be present and the
VCO divider must not be static during VCO calibration.
PLL External Loop Filter
When using the internal VCO, the external loop filter should
be referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 46. The third-
order design shown in Figure 46 usually offers the best
performance. A loop filter must be calculated for each desired
PLL configuration. The values of the components depend upon the
VCO frequency, the K
desired loop bandwidth, and the desired phase margin. The loop
filter affects the phase noise, the loop settling time, and the loop
stability. A basic knowledge of PLL theory is helpful for under-
standing loop filter design. ADIsimCLK can help with the
calculation of a loop filter according to the application
requirements.
VCO
, the PFD frequency, the CP current, the
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When using an external VCO, the external loop filter should be
referenced to ground. An example of an external loop filter for
a PLL using an external VCO is shown in Figure 47.
PLL Reference Inputs
The AD9517 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate single-ended
inputs. The input frequency range for the reference inputs is
specified in Table 2. Both the differential and the single-ended
inputs are self-biased, allowing for easy ac coupling of input signals.
The differential input and the single-ended inputs share the two
pins, REFIN (REF1)/ REFIN (REF2). The desired reference input
type is selected and controlled by Register 0x01C (see
and
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Table 2) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing required of the driver
and overcomes the offset. The differential reference input can be
driven by either ac-coupled LVDS or ac-coupled LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine-wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down, and when their individual power down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
Figure 46. Example of External Loop Filter for a PLL Using the Internal VCO
Figure 47. Example of External Loop Filter for a PLL Using an External VCO
Table 54
).
AD9517-4
AD9517-4
CHARGE
CHARGE
PUMP
PUMP
VCO
31pF
LF
CP
BYPASS
CLK/CLK
CP
C
BP
= 220nF
C1
C1
EXTERNAL
VCO/VCXO
R1
R1
C2
C2
R2
R2
C3
C3
AD9517-4
Table 52