AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9517-4/PCBZ
• Description: BOARD EVALUATION AD9517-4
• Manufacturer: Analog Devices Inc

Specifications of AD9517-4/PCBZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side ( REFIN ) should be
decoupled via a suitable capacitor to a quiet ground.
shows the equivalent circuit of REFIN.
Reference Switchover
The AD9517 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9517 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN ). This feature supports networking
and other applications that require hitless switching of redundant
references. When used in conjunction with the automatic
holdover function, the AD9517 can achieve a worst-case
reference input switchover with an output frequency disturbance as
low as 10 ppm.
When using reference switchover, the single-ended reference
inputs should be dc-coupled CMOS levels and never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing a
false detection of the presence of a reference.
There are several configurable modes of reference switchover.
The switchover can be performed manually or automatically.
Manual switchover is performed either through Register 0x01C
or by using the REF_SEL pin. The automatic switchover occurs
when REF1 disappears. A switchover deglitch feature ensures that
the PLL does not receive rising edges that are far out of alignment
with the newly selected reference.
REFIN
REFIN
REF1
REF2
Figure 48. REFIN Equivalent Circuit
10kΩ
10kΩ
85kΩ
85kΩ
12kΩ
10kΩ
V
V
150Ω
150Ω
S
S
Figure 48
V
S
Rev. B | Page 34 of 80
There are two automatic reference switchover modes, as follows,
that are set in Register 0x01C:
•
•
In automatic mode, REF1 is monitored by REF2. If REF1
disappears (two consecutive falling edges of REF2 without an
edge transition on REF1), REF1 is considered missing. On the
next subsequent rising edge of REF2, REF2 is used as the reference
clock to the PLL. If Register 0x01C[3] = 0b (default), when REF1
returns (four rising edges of REF1 without two falling edges of
REF2 between the REF1 edges), the PLL reference switches back
to REF1. If Register 0x01C[3] = 1b, the user can control when
to switch back to REF1. This is done by programming the part
to manual reference select mode (Register 0x01C[4] = 0b) and
by ensuring that the registers and/or the REF_SEL pin are set to
select the desired reference. Automatic mode can be reactivated
when REF1 is reselected.
Manual switchover requires the presence of a clock on the reference
input being switched to or that the deglitching feature be
disabled (Register 0x01C[7]).
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16383
by writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared with the VCO frequency
divided by the N divider. The frequency applied to the PFD
must not exceed the maximum allowable frequency, which
depends on the antibacklash pulse setting (see Table 2).
The R counter has its own reset. R counter can be reset using
the shared reset bit of the R, A, and B counters. It can also be
reset by a SYNC operation.
VCXO/VCO Feedback Divider N—P, A, B, R
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
where P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9517 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 54, Register 0x16[2:0]. Not all
modes are available at all frequencies (see Table 2).
Prefer REF1. Switch from REF1 to REF2 when REF1
disappears. Return to REF1 from REF2 when REF1 returns.
Stay on REF2. Automatically switch to REF2 if REF1
disappears but do not switch back to REF1 if it reappears.
The reference can be set back to REF1 manually at an
appropriate time.
N = (P × B) + A