AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9517-4/PCBZ
• Description: BOARD EVALUATION AD9517-4
• Manufacturer: Analog Devices Inc

Specifications of AD9517-4/PCBZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When operating the AD9517 in dual modulus mode (P//P + 1),
the equation used to relate input reference frequency to VCO
output frequency is
However, when operating the prescaler in FD mode 1, 2, or 3,
the A counter is not used (A = 0) and the equation simplifies to
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case the previous equation also applies.
By using combinations of DM and FD modes, the AD9517 can
achieve values of N all the way down to N = 1 and up to N =
26,2175. Table 28 shows how a 10 MHz reference input can be
locked to any integer multiple of N.
Note that the same value of N can be derived in different ways, as
illustrated by the case of N = 12. The user can choose a fixed divide
mode P = 2 with B = 6, use the dual modulus mode 2/3 with A = 0,
B = 6, or use the dual modulus mode 4/5 with A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero.
When the prescaler is in dual-modulus mode, the A counter
must be less than the B counter.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that is
Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies
F
(MHz)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
REF
f
f
VCO
VCO
= (f
= (f
R
1
1
1
1
1
1
1
1
1
1
1
1
1
10
1
1
10
REF
REF
/R) × (P × B + A) = f
/R) × (P × B) = f
P
1
2
1
1
1
2
2
2
2
2
8
8
16
32
8
16
32
REF
× N/R
A
X
X
X
X
X
X
0
1
2
1
6
7
7
6
0
14
22
REF
× N/R
1
1
3
4
5
3
3
3
3
4
18
18
9
47
25
16
84
B
N
1
2
3
4
5
6
6
7
8
9
150
151
151
1510
200
270
2710
Rev. B | Page 35 of 80
F
(MHz)
10
20
30
40
50
60
60
70
80
90
1500
1510
1510
1510
2000
2700
2710
VCO
specified in Table 2. This is the prescaler input frequency (VCO
or CLK) divided by P. For example, dual modulus P = 8/9 mode
is not allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9517 B counter is bypassed (B = 1), the A counter
should be set to 0, and the overall resulting divide is equal to the
prescaler setting, P. The possible divide ratios in this mode are
1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an
external VCO/VCXO is used because the frequency range of the
internal VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters— SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously through
the SYNC pin. This function is controlled by Register 0x019[7:6]
(see
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 54.
Table 54
FD
FD
FD
FD
FD
FD
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
Mode
). The
SYNC pin reset is disabled by default.
P = 1, B = 1 (A and B counters are bypassed).
P = 2, B = 1 (A and B counters are bypassed).
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
P = 8 is not allowed (2700 ÷ 8 > 300 MHz).
P = 32 is not allowed (A > B not allowed).
P = 32, A = 22, B = 84.
P = 16 is also permitted.
Comments/Conditions
AD9517-4