AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 53

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AD9517-4/PCBZ

Manufacturer Part Number
AD9517-4/PCBZ
Description
BOARD EVALUATION AD9517-4
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9517-4/PCBZ

Design Resources
High Performance, Dual Channel IF Sampling Receiver (CN0140)
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9517-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 50. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 66)
t
t
DS
S
BIT N
t
HIGH
t
DH
Figure 68. Serial Control Port Timing—Write
t
CLK
Rev. B | Page 53 of 80
t
LOW
BIT N + 1
t
C
AD9517-4

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