AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 58

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AD9517-4/PCBZ

Manufacturer Part Number
AD9517-4/PCBZ
Description
BOARD EVALUATION AD9517-4
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9517-4/PCBZ

Design Resources
High Performance, Dual Channel IF Sampling Receiver (CN0140)
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9517-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9517-4
CONTROL REGISTER MAP DESCRIPTIONS
Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, like this: [5:2].
Table 53. Serial Port Configuration and Part ID
Reg.
Addr
(Hex)
0x000
0x003
0x004
Bits
[7:4]
3
2
1
0
[7:0]
0
Name
Mirrored, Bits[3:0]
Long instruction
Soft reset
LSB first
SDO active
Part ID (read only)
Read back active registers
Description
Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part
is in MSB or LSB first mode (see Bit 1, Register 0x000). User should set bits as follows:
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be 1.
0: 8-bit instruction (short).
1: 16-bit instruction (long) (default).
Soft reset.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to
0 to complete reset operation.
MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
Uniquely identifies the dash version (-0 through -4) of the AD9517
AD9517-0: 0x11
AD9517-1: 0x51
AD9517-2: 0x91
AD9517-3: 0x53
AD9517-4: 0xD3
Select register bank used for a readback.
0: read back buffer registers (default).
1: read back active registers.
Rev. B | Page 58 of 80

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