KS8993-EVAL Micrel Inc, KS8993-EVAL Datasheet
KS8993-EVAL
Specifications of KS8993-EVAL
Related parts for KS8993-EVAL
KS8993-EVAL Summary of contents
Page 1
... May 2005 KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.05 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping at system reset time. ...
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... Commercial temperature range +70 C • Industrial temperature range: – +85 C • Available in 128-pin PQFP with single 2.5V power supply KS8993 Ordering Information Part Number Temperature Range Standard Pb-Free KS8993 KSZ8993 +70 C KS8993I – – + Micrel Package 128-Pin PQFP 128-Pin PQFP May 2005 ...
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... Add TX Disable for Port 1 and port 2, Power down for port 3 and Far end Fault Disable features using MUX[1:2] and TEST[1:2] pins. 2.02 7/2/02 Recommend pull-down on LED[3][3] 2.03 8/29/03 Convert to new format. 2.04 1/24/05 Added reset circuit recommendation. 2.05 5/12/05 Added lead-free part number May 2005 3 Micrel KS8993 ...
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... MII Interface Operation .................................................................................................................................................................. 21 SNI Interface (7-wire) Operation ................................................................................................................................................... 22 Absolute Maximum Ratings .......................................................................................................................................................... 23 Operating Ratings .......................................................................................................................................................................... 23 Electrical Characteristics .............................................................................................................................................................. 23 Timing Diagrams ............................................................................................................................................................................ 24 Reference Circuit ........................................................................................................................................................................... 29 4B/5B Coding ............................................................................................................................................................................ 31 MLT Coding ............................................................................................................................................................................ 32 802.1q VLAN and 802.1p Priority Frame ...................................................................................................................................... 33 Selection of Isolation Transformers ............................................................................................................................................. 34 Selection of Reference Crystals ................................................................................................................................................... 34 Package Outline and Dimensions ................................................................................................................................................ 35 KS8993 4 Micrel May 2005 ...
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... KS8993 System Level Applications The KS8993 can be configured to fit either in a three port 10/ 100 application two port 10/100 network interface with an extra MII or SNI port. This MII/SNI port can be connected to an external processor and used for routing purposes or May 2005 public network access. The major benefits of using the KS8993 are the lower power consumption, unmanaged op- eration, flexible configuration and built in frame buffering ...
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... GND_RX[3] GND 36 FXSD[2] 37 FXSD[3] 38 GND_ANA GND Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional KS8993 (Note 1) Port Pin Function Analog ground I Factory test pin I Factory test pin 1 Ground for receiver I 1 Physical receive signal + (differential Physical receive signal - (differential) ...
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... MII interface, LEDs and other digital I/O Ground for digital circuitry I/O 3 MII input clock O 3 MII collision detect output I/O 3 MII carrier sense I 3 MII collision detect input I 3 MII mode select bit MII mode select bit 0 7 Micrel KS8993 ...
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... VDD 114 P3_PP 115 P2_PP Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional KS8993 (Note 1) Port Pin Function I Selects LED and test modes I Selects LED and test modes I Selects LED and test modes I Selects LED and test modes ...
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... I 3 Port 3 tag removal enable I 2 Port 2 tag removal enable I 1 Port 1 tag removal enable Pwr 1 2.5V for clock recovery circuitry 1 Ground for clock recovery circuitry O Connect to crystal input I Crystal or clock input I 1 Fiber signal detect O Factory test output 9 Micrel KS8993 ...
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... LED[1:3][0] L LED[1:3][1] L LED[1:3][2] L KS8993 Description Differential inputs (receive) for connection to media (transformer or fiber module). Differential outputs (transmit) for connection to media (transformer or fiber module). Fiber signal detect - connect to fiber signal detect output on fiber module. Tie low for 100TX mode. ...
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... Pulled high = enable force flow control feature on port 3, including MII port regardless of auto-negotiation result. Reserved - use float configuration. 11 Micrel Max Length (no tag/tag) 1518/1522 1518/1522 1518/1522 1518/1522 Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable 1536/1536 1536/1536 Not applicable 1536 / 1536 Not applicable KS8993 ...
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... MRXD[3:1] MRXD0 MCOL DISAN3 MIIS[1:0] H KS8993 Description Programs buffer allocation per port at reset time. Use the following table to select the option. Pulled low = 170 buffers (default). Pulled high = adaptive mode. Programs MAC address aging in the address look-up table at reset time. Aging eliminates old entries from the table ...
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... Ports 1 and 2 in VLAN Ports 1 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default) Ports 1 and 2 in VLAN Ports 2 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default) Ports 1 and 3 in VLAN Ports 2 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default) KS8993 Micrel ...
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... VDD_PLL GND_PLL GND_ANA GND_BG VDD_BG VDD VDD_IO GND KS8993 Description Selects queue servicing if using split transmit queues. Use the table below to select desired servicing. Note that this selection effects all split transmit queue ports in the same way. PRSEL 1 0 Priority Selection ...
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... P3_TAGINS P3_TAGRM P2_TAGRM P1_TAGRM VDD_RCV[1] GND_RCV[ FXSD[1] AOUT 1 May 2005 128-Pin PQFP (PQ) 15 Micrel 65 MRXDV MTXCLK MTXER MTXD[0] MTXD[1] MTXD[2] MTXD[3] MTXEN GND VDD DISAN3 PV12 PV13 PV21 FFLOW1# PV23 PV31 PV32 FFLOW2# VMDIS VDD_RCV[3] GND_RCV[3] VDD_RCV[2] GND_RCV[2] TEST[2] TEST[1] 39 KS8993 ...
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... IEEE 802.3. The important factor however is that the KS8993 does adhere to the specified receive signal voltages using the IEEE twisted pair model with a 100 load. The transmit voltage swing can be increased to 2.2V or above by increasing the supply voltage to 2.65V if so desired. ...
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... Power Save Mode The KS8993 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8993 will shutdown most of the internal circuits to save power if there is no link. ...
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... If the DA look-up results is a “match”, the KS8993 will use the destination port information to determine where the packet goes. • If the DA look-up result is a “miss”, the KS8993 will forward the packet to all other ports except the port that received the packet. ...
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... IEEE standard 802.3x. Once the resource is freed up, the KS8993 will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysterisis feature is provided to prevent flow control mechanism from being activated and deactivated too many times ...
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... ARP, the attached router on port 3 will act as an agent and report the MAC address of port 2 to port 1. Then all the unicast traffic between port 1 and port 2 could be switched by KS8993, instead of by the router port. This application could enable “wire speed” switching/routing. This feature is sometimes called “leaky VLAN”. This leaky VLAN does improve the system performance by separating broadcast domains. Note KS8993 does not support “ ...
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... For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII interface for the KS8993 for reverse operation and MTXER is not represented for forward mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC device, but is not appropriate for this configuration ...
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... The SNI (Serial Network Interface) is intended to interface with some controllers used for network layer protocol processing. KS8993 acts like a PHY device to external controllers. This interface can be directly connected to these type of devices. The signals are divided into two groups, one being for transmission and the other being the receive side. The signals involved are described in the table below ...
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... DD_BG DD_PLL , V ) .................................... +2.35V to +2.75V DD ) .................. +2.35V to +2.75V or +3.0V to +3.6V ) ........................... – + Air Flow ................................. 42.91 C +85 C; unless noted. A Min Typ 300 200 V (I/O) DD –0.8 V (I/O) DD –0.4 0. 0.75 0.7 2.2 0.5 –8 Micrel Max Units 330 mA 230 0.4 V 1.0 1E KS8993 ...
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... Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV KS8993 Figure 3. SNI (7-Wire) Input Timing Table 4. SNI (7-Wire) Input Timing Parameters Figure 4. SNI (7-Wire) Output Timing Table 5. SNI (7-Wire) Output Timing Parameters 24 Micrel Min Typ Max Units 100 ns ...
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... KS8993 Figure 5. Reverse MII Timing–Receive Data from MII Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Table 6. Reverse MII Timing–Receive Data from MII Parameters May 2005 (100BaseT) (10BaseT) 25 Micrel Min Typ Max Units 40 ns 400 KS8993 ...
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... KS8993 Figure 6. Reverse MII Timing–Transmit Data to MII Symbol Parameter t Clock Cycle CYC t Output Valid OV Table 7. Reverse MII Timing–Transmit Data to MII Parameters KS8993 (100BaseT) (10BaseT) 26 Micrel Min Typ Max Units 40 ns 400 May 2005 ...
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... KS8993 Figure 7. Forward MII Timing–Receive Data from MII Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Table 8. Forward MII Timing–Receive Data from MII Parameters May 2005 (100BaseT) (10BaseT) 27 Micrel Min Typ Max Units 40 ns 400 KS8993 ...
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... KS8993 Figure 8. Forward MII Timing–Transmit Data to MII Symbol Parameter t Clock Cycle CYC t Output Valid OV Table 9. Forward MII Timing–Transmit Data to MII KS8993 (100BaseT) (10BaseT) 28 Micrel Min Typ Max Units 40 ns 400 May 2005 ...
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... Reset Circuit Diagram Micrel recommendeds the following discrete reset circuit as shown in Figure 9 when powering up the KS8993 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 10 ...
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... It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. KS8993 VCC D1: 1N4148 R D1 10k KS8993 RST C 10µF 30 Micrel May 2005 ...
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... Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Micrel KS8993 ...
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... SA 6 802.1p tag 4 Length 2 Protocol/Data 46 to 1500 Frame CRC 4 ESD 1 Idle Variable KS8993 1010 0011 1000 1110 1001 0100 UUUU UUUU UUUU UUUU 10110101011001011100100110101001101001111111111111 Figure 11. MLT3 coding Description Preamble and Start of Frame Delimiter 48-bit Destination MAC Address 48-bit Source MAC Address ...
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... KS8993 802.1q VLAN and 802.1p Priority Frame The 3-bit of 802.1p priority is embedded into the 802.1q VLAN frame as described below: (bit) May 2005 802.1P Priority Figure 12. 802.1p and 802.1q Frame Format 33 802.1Q VLAN Micrel KS8993 ...
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... An oscillator or crystal with the following typical characteristics is recommended. Characteristics Name Frequency Frequency Tolerance (max.) The following transformer vendors provide pin-to-pin compatible parts for Micrel’s device: Type Transformer only Integrated RJ45 and Transformer KS8993 (Note 1) Value Test Condition 350 H 100mV, 100 KHz, 8mA 0.4 H 1MHz (min ...
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... Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify May 2005 128-Pin PQFP (PQ (408) 474-1000 FAX WEB Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. 35 http://www.micrel.com Micrel KS8993 ...