CLC-CAPT-PCASM National Semiconductor, CLC-CAPT-PCASM Datasheet
CLC-CAPT-PCASM
Specifications of CLC-CAPT-PCASM
Related parts for CLC-CAPT-PCASM
CLC-CAPT-PCASM Summary of contents
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... N CLC-CAPT-PCASM Data Capture Board User’s Guide Section I. Introduction The CLC3790093 Data Capture Board enables simple evaluation of National Semiconductor’s High Speed Analog to Digital Con- verters (ADCs) and the Diversity Receiver Chip Set (DRCS). The Data Capture Board interfaces the outputs of these devices to the standard serial port available on the back of most Personal Computers (PCs) ...
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... CONNECTOR To PC Serial COMM PORT # Hardware 1. CLC3790093 Data Capture Board (CLC-CAPT-PCASM) 2. CLCXXXX Evaluation Board. Several ADC products can be evaluated with this system. Each product has a unique evaluation board which plugs into the data capture board. In order to determine the compatibility of specific ADC evaluation boards to the data capture board, please refer to the “ ...
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... Ain > Ain- + Mid Scale 1000 0000 0000 0000 0000 0000 Ain >> Ain- + Full Scale 1111 1111 1111 1111 1111 1111 CLC5958 Data Analog Input Condition Offset Binary Number Two's Complement Ain- >> Ain - Full Scale 00 0000 0000 0000 10 0000 0000 0000 Ain- > ...
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... Power Up the System Once the WCLK jumper, VCCD jumper, and the DIP switches have been set, (for example, for the CLC5957 we have set WCLK at RDY2, VCCD at +5, and DIP switches 1,2,3,4,5 as ON,ON,ON,OFF,OFF) connect the evaluation board to the data capture board, apply power, clock, and signal to the boards, and connect the serial cable to the PC ...
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... ADC data. The label names are derived from functions in the DRCS and CLC5902, so they might seem out of context for ADC capture uses. Don’t worry about the label names, just make sure you have selected the modes as shown above. Then click on “ ...
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To look at the data that you have just captured, left click on the “Plot_Data” button. If you have collected data with a 12-bit ADC at 52MSPS and a -2dBFS sinewave input at 5MHz, you will see two’s complement data ...
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... It will prove helpful if the user has some familiarity with the CLC5902 data sheet and the Diversity Receiver Evaluation Board User Manual document. Hardware 1. CLC730093 Data Capture Board. (CLC-CAPT-PCASM) 2. CLC730090 DRCS Evaluation Board. (CLC-DRCS-PCASM Power Supply - The DRCS Evaluation and Capture Board combination require +5V at >1A. ...
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... SMA jack. Serial data from the CLC5902 (DDC/AGC) can be configured for “I/Q_Packed, Mux_Mode” in the majority of evaluations (refer to the CLC5902 data sheet or the DRCS Evaluation Board User Manual). For proper operation, a decimation of at least 192 in the DDC is required to complete the transfer of the whole 96-bit word (24-bits each of CHA I & ...
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... DDC in its default output format, the BOUT serial port is disabled. b) The Upper 16-Bits and Lower 16-Bits options enable the CLC5902 DDC’s parallel outputs. In this configuration the DDC parallel output mux is controlled by the FPGA through the 64 pin Euro connector (be sure that the DRCS board SW1 “ ...
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... Control Panel software is not required for these two tests. The DRCS default values contained within the micro-controller with SW2:1-8 = OFF (on DRCS board) will configure the CLC5902 with the proper values. If the power has been applied while in another state or if the user has RESET the micro-controller with a different switch setting, then set the SW2 switches to OFF and press the RESET button on the DRCS Evaluation board ...
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... The Matlab scripts contained on the Evaluation Kit CDROM provide a convenient toolset for evaluation of National’s Diversity Receiver ChipSet (DRCS) and high speed ADCs like the CLC595x family. There are 4 FFT routines and 1 Sine Histogram routine which can be Pinput (dBFS) = -18.1087 called from a user interface menu, “analysis_menu”. Set Output SINAD = 51 ...
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DRCS_Serial “DRCS_ser_fft.m” intended for analysis of the DRCS 24-bit serial out- put data. Fsample is set to a default of 52e6/192 which is the GSM standard output rate of 270.833KS/s. The “search’ option is enabled; therefore, excluding the DC ...
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... CLC-CAPT-PCASM Evaluation Board - Layer 1 CLC-CAPT-PCASM Evaluation Board - Layer 3 CLC-CAPT-PCASM Evaluation Board - Layer 2 CLC-CAPT-PCASM Evaluation Board - Layer 4 13 http://www.national.com ...
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... U1 74)3 SLQ FPGA1 )3*$ 208-pin TQFP 8 EPF10K20 CLC-CAPT-PCASM Schematic Diagram ...
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... National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signifi ...