ISL6521EVAL1 Intersil, ISL6521EVAL1 Datasheet - Page 6

• Manufacturer Part Number: ISL6521EVAL1
• Description: EVALUATION BOARD 1 ISL6521
• Manufacturer: Intersil

Specifications of ISL6521EVAL1

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Power - Output: 13.5W
• Voltage - Output: 1.5V, 2.5V, 3.3V, 1.8V
• Current - Output: 5A, 1A, 1A, 120mA
• Voltage - Input: 4.5 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6521
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

the clamped error amplifier output voltage. As the internal
soft-start voltage increases, the pulse-width on the PHASE
pin increases to reach its steady-state duty cycle at time T2.
Also at time T2, the error amplifier references of the linear
controllers, ramp to their final value bringing all outputs
within regulation limits.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against a shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (r
triggers a shutdown of the V
internal soft-start initiates a number of soft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify a UV event on one of the linears, at time T1,
the clock regulator (V
overcurrent event, resulting in a UV condition. Similarly, after
0V
0V
(1V/DIV)
(0.5V/DIV)
+5V
T0
FIGURE 1. SOFT-START INTERVAL
T1
DS(ON)
OUT2
to monitor the current for protection
T2
) is also subjected to an
V
V
V
OUT1
V
OUT4
OUT3
OUT1
OUT2
TIME
6
(3.3V)
(1.5V)
(1.8V)
(2.5V)
output. As a result, its
DS(ON)
sensing)
ISL6521
three soft-start periods, the fourth cycle initiates a ramp-up of
this linear output at time T3. One soft-start period after T3,
the linear output is within regulation limits. UV glitches less
than 1µs (typically) in duration are ignored.
Overcurrent protection is performed on the synchronous
switching regulator on a cycle-by-cycle basis. OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).
A resistor (R
the PWM converter. As shown in Figure 3, the internal
40µA current sink (I
R
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V
V
overcurrent latch. Both V
to V
track the variations of V
overcurrent function will trip at a peak inductor current
(I
I
PEAK
SET
PEAK)
0V
OCSET
FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION
IN
(0.5V/DIV.)
UV MONITORING
, the overcurrent comparator trips to set the
and a small capacitor across R
=
determined by:
T0
I
--------------------------------------------------- -
(V
OCSET
V
SET
OUT1
OCSET
RESPONSE
r
DS ON
) that is referenced to V
T1
×
(
R
OCSET
) programs the overcurrent trip level for
V
OCSET
)
OUT2
IN
INACTIVE
SET
V
SOFT-START
OUT2
due to MOSFET switching. The
FUNCTION
) develops a voltage across
TIME
V
V
OUT4
OUT3
and V
(2.5V)
(3.3V)
(1.8V)
DS(ON)
OCSET
V
OUT1
IN
T2
. The DRIVE
DS(ON)
(1.5V)
are referenced
helps V
ACTIVE
T3
) exceeds
T4
OCSET