HW-V5-ML525-UNI-G Xilinx Inc, HW-V5-ML525-UNI-G Datasheet

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HW-V5-ML525-UNI-G

Manufacturer Part Number
HW-V5-ML525-UNI-G
Description
EVAL PLATFORM ROCKET IO VIRTEX-5
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Type
FPGAr
Datasheet

Specifications of HW-V5-ML525-UNI-G

Contents
ML52x Platform, Power Supply, Cables and Documentation
For Use With/related Products
Virtex™-5 LXT
For Use With
HW-XGI-SCLK-G - MODULE SUPER CLOCKHW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-NQSL-G - NQSL NELCO QUAD SERIAL LOOPHW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-SDRAM - EXPANSION MOD SDRAM BERG-SDRAM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HW-V5-ML525-UNI-G-J
Manufacturer:
XILINX
0
ML52x User Guide
Virtex-5 FPGA RocketIO
Characterization Platform
UG225 (v2.1) August 4, 2010
R
0402527-03

Related parts for HW-V5-ML525-UNI-G

HW-V5-ML525-UNI-G Summary of contents

Page 1

ML52x User Guide Virtex-5 FPGA RocketIO Characterization Platform UG225 (v2.1) August 4, 2010 R 0402527-03 ...

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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...

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Table of Contents Preface: About This Guide Additional Documentation Additional Support Resources Typographical Conventions Online Document . . . . . . . . . . . . . . . . . . . . . . . . ...

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R ML52x User Guide UG225 (v2.1) August 4, 2010 ...

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R About This Guide This user guide describes the features and operation of the Virtex of RocketIO™ characterization platforms. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. • Virtex-5 Family Overview The features and product selection ...

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Preface: About This Guide • Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT platforms used for PCI Express® designs. • XtremeDSP Design Considerations ...

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R Typographical Conventions This document uses the following conventions. An example illustrates each convention. Convention Italic font Underlined Text Online Document This document uses the following conventions. An example illustrates each convention. Convention Blue text Red text Blue, underlined text ...

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Preface: About This Guide 8 www.xilinx.com R ML52x User Guide UG225 (v2.1) August 4, 2010 ...

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R ML52x User Guide Package Contents • ML52x RocketIO characterization platform (referred to as the ML52x platform) • UG225, ML52x User Guide: Virtex-5 RocketIO Characterization Platform • SMA-to-SMA cable assemblies: • Four 24-inch cable assemblies • Two 12-inch cable assemblies ...

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Related Documents Related Documents Prior to using the ML52x platforms, users should be familiar with Xilinx resources. See “References,” page 35 following locations for additional documentation on Xilinx tools and solutions. • EDK: www.xilinx.com/edk ® • ISE Design Tools: • ...

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R • General purpose DIP switches, LEDs, and pushbutton switches • 128 MB of DDR2 Memory Figure 1 shows the block diagram of the board. X-Ref Target - Figure 1 GTP/GTX Transceiver SMA System ACE Controller UART ...

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Detailed Description Detailed Description The ML52x platform shown in guide. Each feature is detailed in the numbered sections that follow. Note: The image might not reflect the current revision of the board. X-Ref Target - Figure ...

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R 1. Power Switch The board has onboard power supplies controlled by the power switch. When the V5 LED is lit, this indicates the board is powered. On Position In the ON position, the power switch enables delivery of all ...

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Detailed Description Table 2: Onboard Regulation: Voltage, Current, Jacks, and Jumpers (Cont’d) Power Supply Max Current Typical Name Rating Voltage VCCO 6.0A 2.5V VCCAUX 3.0A 2.5V GND N/A N/A X-Ref Target - Figure 3 2.5V 1.0V Regulator Regulator Jack Jack ...

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R listed in Table external supply on its corresponding supply jack. Table 3: Power Supply Module Jumpers Typical Voltage GTP/GTX Power Max Current (1) Supply Name Rating LXT MGTAVCC 3.0A 1.0V AVCCPLL 1.5A 1.2V AVTTTX 1.5A 1.2V AVTTRX 1.5A 1.2V ...

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Detailed Description 7. System ACE Controller An onboard System ACE controller allows the user to store multiple configuration files on a CompactFlash card. These configuration files can be used to program the FPGA. 8. Reset Switch (Active-Low) The active-Low reset ...

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R 11. System ACE MPU Port The 8-bit MPU port of the System ACE controller implemented on the ML52x series boards and the port connection to the DUT are shown in System ACE MPU port see System ACE CompactFlash Solution ...

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Detailed Description 12. Oscillator Sockets The ML52x platform has two oscillator sockets, each wired for standard LVCMOS-type oscillators. These connect to the DUT clock pins as shown in accept both half- and full-sized oscillators and are powered by 3.3V or ...

Page 19

R 15. User LEDs (Active-High) There are 16 active-High LEDs, as shown I/O pins on the DUT. These LEDs can be used to indicate status or any other purpose the user sees fit. Table 10: User LEDs Top Column Ref ...

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Detailed Description 16. User DIP Switches (Active-High) There are 16 active-High DIP switches, as shown in connected to user I/O pins on the DUT. These pins can be used to set control pins or any other purpose the user sees ...

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R 18. DDR2 Memory The DDR2 memory interface on the ML52x board consists of four 256-Mbit DDR2 SDRAM chips (Micron MT47H16M16BG-3:B or Infineon HYB18T256160AF) for a total of 1-Gbit (128-MB) capacity. The pins conform to the SSTL_1.8V standard and must ...

Page 22

Detailed Description Table 15: DDR2 Connections to the DUT (Cont’d) Pin Name D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 ...

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R Table 15: DDR2 Connections to the DUT (Cont’d) Pin Name D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 ...

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Detailed Description Table 15: DDR2 Connections to the DUT (Cont’d) Pin Name DQM4 DQM5 DQM6 DQM7 DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# ODT RAS# WE# 24 ML521 ML523 AD14 AG30 ...

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R 19. GTP/GTX Transceiver Clock Input SMAs The ML52x series platforms provide differential SMAs that allow connection to an external function generator for all GTP/GTX transceiver reference clock inputs of the DUT. These SMAs connect to the DUT reference clock ...

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Detailed Description 20. GTP/GTX Transceiver Pins All DUT GTP/GTX transceiver pins are connected to differential SMA pairs. The transceiver pins and their corresponding SMA are shown in Table 17: GTP/GTX Transceiver Pins REF DES J56 J54 J53 J55 J51 J52 ...

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R Table 17: GTP/GTX Transceiver Pins (Cont’d) REF DES J29 J30 J76 J75 J73 J74 J71 J72 J69 J70 J96 J95 J93 J94 J91 J92 J89 J90 J66 J65 J63 J64 J61 J62 J59 J60 J86 J85 J83 J84 J81 ...

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Detailed Description Table 17: GTP/GTX Transceiver Pins (Cont’d) REF DES J154 J156 J152 J153 J150 J151 J148 J149 J174 J176 J172 J173 J170 J171 J168 J169 J158 J145 J144 J157 J142 J143 J21 J141 J178 J165 J164 J177 J162 J163 ...

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R 21. RS-232 Port Pins The RS-232 port pin connections to the DUT are as shown in in DTE mode as shown in Table 18: RS-232 Port Pins Pin Name TXD RTS RXD CTS X-Ref Target - Figure 4 22. ...

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Detailed Description Table 19: Top View of PCB (Cont’d) Row The XGI pin ...

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R Table 20: XGI Pin Connections to the DUT (J113 and J135) XGI Pin # Description XGI Pin # F1 GND E2 F3 GND E4 F5 GND E6 F7 GND E8 F9 GND E10 F11 GND E12 F13 GND E14 ...

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Detailed Description Table 21: XGI Pin Connections to the DUT (J136) XGI Pin # C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 ...

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R Table 22: XGI Pin Connections to the DUT (J118) XGI Pin # B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 ...

Page 34

Detailed Description Table 23 defines the default jumper positions set by the factory. Table 23: Default Jumper Positions Ref Des J112 J110 J111 J127 J5 J24 J126 J114 J115 J116 J117 J128 J129 J131 J132 J137 J138 J139 J140 J130 ...

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R References Users should be familiar with the following Xilinx documents: 1. DS080, System ACE CompactFlash Solution 2. UG091, Xilinx Generic Interface (XGI) SuperClock Module User Guide 3. UG190, Virtex-5 FPGA User Guide 4. UG196, Virtex-5 FPGA RocketIO GTP Transceiver ...

Page 36

References 36 www.xilinx.com R ML52x User Guide UG225 (v2.1) August 4, 2010 ...

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