FS-9003 Digi International, FS-9003 Datasheet
FS-9003
Specifications of FS-9003
Related parts for FS-9003
FS-9003 Summary of contents
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... JTAG-Booster for Intel XScale P.O: Box 1103 Kueferstrasse 8 Tel. +49 (7667) 908-0 sales@fsforth.de • D-79200 Breisach, Germany • D-79206 Breisach, Germany • Fax +49 (7667) 908-200 • http://www.fsforth.de ...
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... FS FORTH-SYSTEME GmbH Postfach 1103, D-79200 Breisach, Germany Release of Document: Author: Filename: Program Version: All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of FS FORTH-SYSTEME GmbH. 2 September 12, 2003 Dieter Fögele JTAG_XScaleb.doc 4.xx ...
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Table of Contents 1. General ..........................................................................................................5 1.1. Ordering Information ............................................................................6 1.2. System Requirements ..........................................................................6 1.3. Contents of Distribution Disk ................................................................7 1.4. Connecting your PC to the target system .............................................8 1.5. First Example with Intel PXA210/250.................................................. 10 1.6. First Example with ...
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De-Installation version 5.x/6.x: ........................................................... 89 4 JTAG_XScaleb.doc ...
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General The programs JTAG250.EXE, JTAG255.EXE, JTAG321.EXE and JTAG425 use the JTAG port of the Intel XScale processors in conjunction with the small JTAG- Booster: to program data into flash memory to verify and read the contents of a flash ...
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Ordering Information The following related products are available 9003 JTAG-Booster Intel XScale, 3.3V, PXA210/250, PXA255/26X, IOP321, PXA425 DOS/Win9x/WinNT/Win2000/WinXP, delivered with adapter type 285 1.2. System Requirements To successfully run this tool the following requirements must be met: MSDOS, WIN3.x, ...
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Contents of Distribution Disk JTAG250.EXE Tool for Intel PXA210/250 JTAG250.OVL JTAG250.INI Template configuration file for Intel PXA210/250. See chapter 1.11 "Initialization file JTAGxxx.INI" JTAG255.EXE Tool for Intel PXA255/26x JTAG255.OVL JTAG255.INI Template configuration file for Intel PXA255/26x. See chapter 1.11 ...
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... Pin 7 is the target’s TDO pin and is an input on the JTAG-Booster’s side. The 3.3V version of the JTAG-Booster (FS part number 285) is delivered together with this package. Don’t use the 5V version of the JTAG-Booster (FS part number 227) with a 3.3V target. Don’t apply 5V to the 3.3V version of the JTAG-Booster! Your target must be able to power the JTAG-Booster, it draws about 100mA ...
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The utility is started with the general command line format: JTAGxxx JTAGxxx /function [filename] [/option_1] ... [/option_n]. Note that the function must be the first argument followed (if needed) by the filename. If you want to cancel execution of JTAGxxx, ...
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... In the following simple example it is assumed that the JTAG-Booster is connected to LPT1 of your PC and target power is on. Typing JTAG250 /P MYAPP.BIN at the DOS prompt results in the following output: JTAG250 --- JTAG utility for Intel PXA210/250 Copyright FS FORTH-SYSTEME GmbH, Breisach Version 4.xx of mm/dd/yyyy (1) Configuration loaded from file JTAG250.INI (2) Target: Generic Target (3) ...
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... The position of the JTAG instruction register of the Intel XScale is assumed to be zero, if not specified in the command line (see option /IROFFS=). (10) The real length of the boundary scan register is displayed here and compared with the boundary scan register length of a Intel PXA210/250. (11) Two Flashes Intel 28F128 selected with CS0# where found. ...
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In this example one block must be erased. 12 JTAG_XScaleb.doc ...
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... In the following simple example it is assumed that the JTAG-Booster is connected to LPT1 of your PC and target power is on. Typing JTAG255 /P MYAPP.BIN at the DOS prompt results in the following output: JTAG255 --- JTAG utility for Intel PXA255/26x Copyright FS FORTH-SYSTEME GmbH, Breisach Version 4.xx of mm/dd/yyyy (1) Configuration loaded from file JTAG255.INI (2) Target: Generic Target (3) ...
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... The position of the JTAG instruction register of the Intel XScale is assumed to be zero, if not specified in the command line (see option /IROFFS=). (10) The real length of the boundary scan register is displayed here and compared with the boundary scan register length of a Intel PXA255/26x. (11) Two Flashes Intel 28F128 selected with CS0# where found. ...
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... In the following simple example it is assumed that the JTAG-Booster is connected to LPT1 of your PC and target power is on. Typing JTAG321 /P MYAPP.BIN at the DOS prompt results in the following output: JTAG321 --- JTAG utility for Intel IOP321 Copyright FS FORTH-SYSTEME GmbH, Breisach Version 4.xx of mm/dd/yyyy (1) Configuration loaded from file JTAG321.INI (2) Target: Generic Target (3) ...
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... The position of the JTAG instruction register of the Intel XScale is assumed to be zero, if not specified in the command line (see option /IROFFS=). (9) The real length of the boundary scan register is displayed here and compared with the boundary scan register length of a Intel IOP321. ...
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... In the following simple example it is assumed that the JTAG-Booster is connected to LPT1 of your PC and target power is on. Typing JTAG425 /P MYAPP.BIN at the DOS prompt results in the following output: JTAG425 --- JTAG utility for Intel IXP425 Copyright FS FORTH-SYSTEME GmbH, Breisach Version 4.xx of mm/dd/yyyy (1) Configuration loaded from file JTAG425.INI (2) Target: Generic Target with IXP425 (3) ...
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... The position of the JTAG instruction register of the Intel XScale is assumed to be zero, if not specified in the command line (see option /IROFFS=). (10) The real length of the boundary scan register is displayed here and compared with the boundary scan register length of a Intel IXP425. (11) One Flash Intel 28F128 selected with EX_CS0# was found. ...
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Trouble Shooting Avoid long distances between your Host-PC and the target. If you are using standard parallel extension cable, the JTAG-BOOSTER may not work. Don't use Dongles between the parallel port and the JTAG-BOOSTER. Switch off all special modes ...
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... Configuration file XYZ not found. The file specified with the option /INI= wasn't found. Device offset out of range The value specified with the option /OFFSET= is greater than the size of the detected flash device. Disk full Writing a output file was aborted as a result of missing disk space. ...
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Error creating file: The output file could not be opened. Please check free disk space or write protection. Error: Pin-Name is an output only pin The specified pin cannot be sampled. Check the command line. Check the initialization file. Error: ...
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Input file is empty: Files with zero length are not accepted " " is undefined Please check the syntax in your configuration file. (See chapter 1.11 “Initialization file JTAGxxx.INI”). LPTx not installed The LPT port specified with /LPTx cannot be ...
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... Intel XScale (7 bits for the IXP425) The sum of all instruction register bits in the JTAG chain does not fit to the Intel XScale. Check the target connection. Check the target CPU type. Check the settings for /IROFFS= and /CPUPOS there are several parts in the JTAG chain. JTAG_XScaleb.doc ...
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... The length of the boundary scan register of the selected part (if there are more than one in the chain) does not fit to the Intel XScale. Check the target connection. Check the target CPU type. Check the settings for /IROFFS= and /CPUPOS there are several parts in the JTAG chain. ...
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Initialization file JTAGxxx.INI This file is used to define the default direction and level of all CPU signals. This file must be carefully adapted to your design with the Intel XScale. The Target- Entry is used to identify your ...
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Sample File JTAG250.INI: // Description file for Intel PXA210/250 Target: Generic Target // Adapt this file carefully to your design!! // All chip select signals are set to output and inactive. // The chip selects for the external PC-Card are ...
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BITCLK, AC97 bit clock output // BITCLK, I2S bit clock input // BITCLK, I2S bit clock output GPIO29 Inp // SDATA_IN0, AC97 sdata input 0 // SDATA_IN, I2S sdata input GPIO30 Inp // SDATA_OUT, AC97 sdata output // SDATA_OUT, ...
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GPIO59 Inp // L_DD1, LCD data pin 1 GPIO60 Inp // L_DD2, LCD data pin 2 GPIO61 Inp // L_DD3, LCD data pin 3 GPIO62 Inp // L_DD4, LCD data pin 4 GPIO63 Inp // L_DD5, LCD data pin 5 ...
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MD7 Inp // Memory Data Bus MD8 Inp // Memory Data Bus MD9 Inp // Memory Data Bus MD10 Inp // Memory Data Bus MD11 Inp // Memory Data Bus MD12 Inp // Memory Data Bus MD13 Inp // Memory ...
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Group 208: All pins in this group must be set to the same direction // These pins are tristateable, but can not be read back SDCLK1 Out,Lo // SDCS0# Out,Hi // DQM0 Out,Lo // SDRAM DQM0 DQM1 Out,Lo // ...
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The following pins are output only pins. // Setting to input (tristate) one of these pins results in an error. PWR_EN Out,Hi // Enable ext. power supply RESET_OUT# Out,Lo // Reset ouput ACRESET# Out,Lo // AC97 audio port reset ...
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Sample File JTAG255.INI: // Description file for Intel PXA255/26x Target: Generic Target // Adapt this file carefully to your design!! // All chip select signals are set to output and inactive. // The chip selects for the external PC-Card are ...
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GPIO28 Inp // BITCLK, AC97 bit clock input // BITCLK, AC97 bit clock output // BITCLK, I2S bit clock input // BITCLK, I2S bit clock output GPIO29 Inp // SDATA_IN0, AC97 sdata input 0 // SDATA_IN, I2S sdata input GPIO30 ...
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HWCTS#, Hardware UART clear to send GPIO51 Inp // PIOW#, Card Space I/O write // HWRTS#, Hardware UART request to send GPIO52 Out,Hi // PCE1#. Card Space card enable 1, !!! GPIO53 Out,Hi // PCE2#, Card Space card enable ...
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GPIO80 Out,Hi // CS4#, chip select 4 GPIO81 Inp // NSSPSCLK, Network synchronous serial port (output) GPIO82 Inp // NSSPSFRM, Network synchronous serial frame signal (output) GPIO83 Inp // NSSPTXD, Network synchronous serial port transmit (output) GPIO84 Inp // NSSPRXD, ...
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MD24 Inp // Memory Data Bus MD25 Inp // Memory Data Bus MD26 Inp // Memory Data Bus MD27 Inp // Memory Data Bus MD28 Inp // Memory Data Bus MD29 Inp // Memory Data Bus MD30 Inp // Memory ...
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MA16 Out,Lo // MA17 Out,Lo // MA18 Out,Lo // MA19 Out,Lo // MA20 Out,Lo // MA21 Out,Lo // MA22 Out,Lo // MA23 Out,Lo // MA24 Out,Lo // MA25 Out, Group 81: All pins in this group must be ...
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Sample File JTAG321.INI: // Description file for Intel IOP321 Target: Generic Target // Adapt this file carefully to your design!! // All chip select signals are set to output and inactive. // All signals should be defined. Undefined signals are ...
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AD21 Inp // PBI Address/Data Bus AD22 Inp // PBI Address/Data Bus AD23 Inp // PBI Address/Data Bus // Group 42: All pins in this group must be set to the same direction // These pins are bidirectional AD8 Inp ...
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Group 53: All pins in this group must be set to the same direction // These pins are tristateable, but can not be read back BE0# Out,Lo // PBI Byte Enable for AD0..7 for 32/16Bit // PBI Address Bit ...
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P_AD63 Inp // // Group 112: All pins in this group must be set to the same direction // These pins are bidirectional P_AD0 Inp // PCI Address/Data P_AD1 Inp // P_AD2 Inp // P_AD3 Inp // P_AD4 Inp // ...
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Group 114: All pins in this group must be set to the same direction // These pins are bidirectional P_CBE4# Inp // PCI Byte Enable P_CBE5# Inp // PCI Byte Enable P_CBE6# Inp // PCI Byte Enable P_CBE7# Inp ...
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SA4 Out,Lo // SDRAM Memory Address SA5 Out,Lo // SDRAM Memory Address SA6 Out,Lo // SDRAM Memory Address SA7 Out,Lo // SDRAM Memory Address SA8 Out,Lo // SDRAM Memory Address SA9 Out,Lo // SDRAM Memory Address SA10 Out,Lo // SDRAM ...
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DQ26 Inp // SDRAM Data DQ27 Inp // SDRAM Data DQ28 Inp // SDRAM Data DQ29 Inp // SDRAM Data DQ30 Inp // SDRAM Data DQ31 Inp // SDRAM Data // Group 232: All pins in this group must be ...
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DQ61 Inp // SDRAM Data DQ63 Inp // SDRAM Data // Group 233: All pins in this group must be set to the same direction // SCB0..7 are bidirectional // SDQM8 is tristateable, but can not be read back SCB0 ...
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GPIO7 Inp // = SCL0 RDYRCV# Out,Hi // PBI Read/Recover P_ACK64# Inp // PCI Bus Acknowledge 64 bit Transfer P_REQ64# Inp // PCI Bus Request 64 bit P_PAR64 Inp // PCI Bus Upper DWORD Parity P_SERR# Inp // PCI Bus ...
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XINT3# Inp // External Interrupt Request HOLD Inp // PBI HOLD P_M66EN Inp // PCI 66MHz enable P_GNT# Inp // PCI Bus Grant input P_RST# Inp // PCI Reset Input P_IDSEL Inp // PCI Initialization Device Select P_CLK Inp // ...
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Sample File JTAG425.INI: // Description file for Intel IXP425 Target: Generic Target // Adapt this file carefully to your design!! // All chip select signals are set to output and inactive. // All signals should be defined. Undefined signals are ...
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The following pins are complete bidirectional pins // These pins are switched between output/active and input/tristate during // programming of Flash-EPROMs EX_DATA15 Inp // Expansion Bus Data EX_DATA14 Inp // EX_DATA13 Inp // EX_DATA12 Inp // EX_DATA11 Inp // ...
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HSS_RXCLK0 Inp // High Speed Serial Receive Clock 0 PCI_GNT0# Inp // PCI Arbitration Grant PCI_REQ0# Inp // PCI Arbitration Request PCI_SERR# Inp // PCI System Error PCI_PERR# Inp // PCI Parity Error PCI_DEVSEL# Inp // PCI Device Select PCI_STOP# ...
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PCI_AD3 Inp // PCI_AD2 Inp // PCI_AD1 Inp // PCI_AD0 Inp // SDM_DATA31 Inp // SDRAM Data SDM_DATA30 Inp // SDM_DATA29 Inp // SDM_DATA28 Inp // SDM_DATA27 Inp // SDM_DATA26 Inp // SDM_DATA25 Inp // SDM_DATA24 Inp // SDM_DATA23 Inp ...
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GPIO10 Inp // GPIO9 Inp // GPIO8 Inp // GPIO7 Inp // GPIO6 Inp // GPIO5 Inp // GPIO4 Inp // GPIO3 Inp // GPIO2 Inp // GPIO1 Inp // UTP_IP_ADDR4 Inp // Utopia Receive PHY Address UTP_IP_ADDR3 Inp // ...
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SDM_ADDR10 Out,Lo // SDM_ADDR9 Out,Lo // SDM_ADDR8 Out,Lo // SDM_ADDR7 Out,Lo // SDM_ADDR6 Out,Lo // SDM_ADDR5 Out,Lo // SDM_ADDR4 Out,Lo // SDM_ADDR3 Out,Lo // SDM_ADDR2 Out,Lo // SDM_ADDR1 Out,Lo // SDM_ADDR0 Out,Lo // EX_ALE Out,Lo // Expansion Bus Address Latch ...
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PCI_CLKIN Inp // PCI_REQ3# Inp // PCI_REQ2# Inp // PCI_REQ1# Inp // PCI_IDSEL Inp // EX_RDY3# Inp // EX_RDY2# Inp // EX_RDY1# Inp // EX_RDY0# Inp // EX_CLK Inp // EX_IOWAIT# Inp // CTS1# Inp // RXDATA1 Inp // CTS0# ...
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ETH_RXDATA0_2 Inp // ETH_RXDATA0_1 Inp // ETH_RXDATA0_0 Inp // ETH_RXDV0 Inp // ETH_TXCLK0 Inp // JTAG_XScaleb.doc 55 ...
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Supported flash devices Type JTAGxxx /LIST [optionlist] to get a online list of all flash types which could be used with the /DEVICE= option. See separate file JTAG_V4xx_FLASHES.pdf to get a complete list of supported flash types. 56 JTAG_XScaleb.doc ...
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... When you start JTAGxxx.EXE without any parameters the following help screen with all possible functions and options is displayed: JTAGxxx --- JTAG utility for Intel XScale Copyright © FS FORTH-SYSTEME GmbH, Breisach Version 4.xx of mm/dd/yyyy Programming of Flash-EPROMs and hardware tests on targets with the Intel XScale. ...
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... Besides the standard JTAG-Booster interface there are several simple "Parallel- Port-JTAG" interfaces supported. With this interfaces the programming performance, of course, is reduced. 58 /CS2 /CS3 /NOWRSETUP /TOP /P /NODUMP /LPT1 /LPT2 /16BIT /8BIT /FILE-OFFSET= /FO= /DEVICE-BASE= /DB= /IROFFS= /CPUPOS= /I2CDAT= /I2CDATI= /OUT= /INI= JTAG_XScaleb.doc /CS4 /BYTE-MODE /NOERASE /LPT3 ...
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... This pin must be specified as output in the initialization file. /IROFFS= Specifies the position of the Intel XScale instruction register within the JTAG chain. In most cases this option is not needed. Default: /IROFFS=0 /CPUPOS= Specifies the position of the Intel XScale within the JTAG chain. Default: /CPUPOS=0 JTAG_XScaleb ...
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Program a Flash Device Usage: JTAGxxx /P filename [optionlist] The specified file is programmed into the flash memory. The flash status is polled after programming of each cell (cell= bit, depending on current data bus width). ...
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... Abbreviation: /O= /TOP If the option /TOP is used the option /OFFSET= specifies the address where the programming ends (plus one) instead of the starting address. This option is very important for Intel CPU architectures, because target execution always starts at the top of the address space. ...
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The number of programmed bytes may be limited to LENGTH LENGTH is specified the whole file is programmed. Default: /LENGTH=4000000 (64 MByte) Abbreviation: /L= /NODUMP In case of a verify error the contents of the flash memory ...
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Examples: JTAGxxx /P ROMDOS.ROM /L=20000 /TOP This example programs up to 128 Kbytes of the file ROMDOS.ROM (with i.e. 512 Kbytes) to the top of the boot flash memory. JTAGxxx /P CE.ROM /32BIT /CS1 This example programs the file CE.ROM ...
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... See function /P (Chapter 2.1) 2 /DEVICE-BASE=hhhhhh See function /P (Chapter 2.1) /OFFSET=hhhhhh Reading of the flash memory starts at an offset of hhhhhh relative to the start address of the flash device. If the offset is negative, the offset specifies a address relative to the end of the flash device. See also option /TOP. Default: ...
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... If the option /TOP is used the option /OFFSET= specifies the address where reading ends (plus one) instead of the starting address. /LENGTH=hhhhhh The number of read bytes may be limited to LENGTH LENGTH is specified the whole flash device is read (if no offset is specified). /CS0 /CS1 /CS2 /CS3 /CS4 /CS5 See function /P (Chapter 2 ...
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... See function /P (Chapter 2.1) /8BIT /16BIT /32BIT See function /P (Chapter 2.1) /BYTE-MODE See function /P (Chapter 2.1) /NOMAN See function /P (Chapter 2.1) /DEVICE-BASE=hhhhhh See function /P (Chapter 2.1) /OFFSET=hhhhhh See function /P (Chapter 2.1) /TOP See function /P (Chapter 2.1) /FILE-OFFSET=hhhhhh See function /P (Chapter 2.1) 66 JTAG_XScaleb.doc ...
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See function /P (Chapter 2.1) /NODUMP See function /P (Chapter 2.1) /CS0 /CS1 /CS2 /CS3 /CS4 /CS5 See function /P (Chapter 2.1) /NOWRSETUP See function /P (Chapter 2.1) Please note: In the function /V write cycles are needed to ...
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... Default: /OFFSET=0 Abbreviation: /O= 3 /DEVICE-BASE=hhhhhh The device start address is used as an additional offset. This gives the function /DUMP the same behavior as function /P /V and /R. Default: /DEVICE-BASE=0 Abbreviation: /DB= /TOP If the option /TOP is used the option /OFFSET= specifies the address where ...
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Example: JTAGxxx /DUMP This example makes a memory dump of the first 256 bytes of the Boot-EPROM. JTAG_XScaleb.doc 69 ...
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... The programming starts at an offset of hhhhhh relative to the start address of the I²C-Device. Default: /OFFSET=0 Abbreviation: /O= /FILE-OFFSET=hhhhhh If FILE-OFFSET is specified, the first hhhhhh bytes of the file are skipped and not programmed to target. Default: /FILE-OFFSET=0 Abbreviation: /FO= 70 (if option /I2CBIG omitted) (if option /I2CBIG specified) ...
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The number of programmed bytes may be limited to LENGTH LENGTH is specified the whole file is programmed. Abbreviation: /L= /NODUMP In case of a verify error the contents of the I²C-Device is written to a file ...
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... Options: /I2CBIG This option must be the first option after the filename. See function /PI2C (Chapter 2.5) /DEVICE-BASE=hhhhhh See function /PI2C (Chapter 2.5) /OFFSET=hhhhhh Reading of the I²C-Device starts at an offset of hhhhhh relative to the start address of the I²C-Device. Default: /OFFSET=0 Abbreviation: /O= /LENGTH=hhhhhh The number of read bytes must be specified otherwise an error message occurs. ...
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Example: JTAGxxx /RI2C EEPROM.CFG /I2CCLK=GP26 /I2CDAT=GP27 /L=100 This example reads 256 bytes from a serial EEPROM to the file EEPROM.CFG. The serial EEPROM is connected to the pins CP26 and GP27 of the Intel XScale. JTAG_XScaleb.doc 73 ...
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... This option must be the first option after the filename. See function /PI2C (Chapter 2.5) /DEVICE-BASE=hhhhhh See function /PI2C (Chapter 2.5) /OFFSET=hhhhhh See function /PI2C (Chapter 2.5) /FILE-OFFSET=hhhhhh See function /PI2C (Chapter 2.5) /LENGTH=hhhhhh See function /PI2C (Chapter 2.5) /NODUMP See function /PI2C (Chapter 2.5) /I2CCLK=pin_name See function /PI2C (Chapter 2 ...
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See function /PI2C (Chapter 2.5) Example: JTAGxxx /VI2C EEPROM.CFG /I2CCLK=GP26 /I2CDAT=GP27 This example verifies 256 bytes from a serial EEPROM with the file EEPROM.CFG. The serial EEPROM is connected to the pins CP26 and GP27 of the Intel XScale. ...
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... A Hex-Dump of an I²C-Device is printed on the screen, if not redirected to file or device. Options: /I2CBIG This option must be the first option. See function /PI2C (Chapter 2.5) /DEVICE-BASE=hhhhhh See function /PI2C (Chapter 2.5) 4 /OFFSET=hhhhhh The memory dump starts at an offset of hhhhhh. Default: /OFFSET=0 Abbreviation: /O= /LENGTH=hhhhhh Default: /LENGTH=100 Abbreviation: /L= /I2CCLK=pin_name Specifies the CPU pin used for serial clock output ...
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Specifies the CPU pin used for serial data input. Pin_name must specify a input pin otherwise an error message occurs. Example: JTAGxxx /DUMPI2C /I2CCLK=FLAG0 /I2CDAT=FLAG1 This example makes a memory dump of the first 100h bytes of a serial ...
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Toggle CPU pins Usage: JTAGxxx /BLINK /PIN=pinname [optionlist] This command allows to test the hardware by blinking with LEDs or toggling CPU signals. Faster signals can be generated by setting the delay option to zero. This can be a ...
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Polling CPU pins Usage: JTAGxxx /PIN? /PIN=pinname [optionlist] This command allows to test the hardware by polling CPU signals. Please Note: Not every pin of the Intel XScale may be specified as an input pin. Options: /PIN=pin_name CPU pin ...
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Polling CPU pins while the CPU is running Usage: JTAGxxx /SAMPLE /PIN=pinname [optionlist] This command is similar to the function /PIN?. But with this function any pin can be observed, independent of the pin direction. Furthermore the CPU remains ...
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Show status of all CPU pins while the CPU is running Usage: JTAGxxx /SNAP [optionlist] This function is similar to the function /SAMPLE, but displays the status of all CPU pins on the screen. The CPU remains in normal ...
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Sample output: This is a sample output for a Intel PXA210/250 | 0 GPIO0 | 1 GPIO1 | 1 GPIO4 | 1 GPIO5 | 1 GPIO8 | 1 GPIO9 | 1 GPIO12 | 1 GPIO13 | 1 GPIO16 | 1 ...
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MA23 | 0 MA24 | 0 TESTCLK | 1 VDD_FAULT BOOT_SEL1 | 0 BOOT_SEL2 JTAG_XScaleb.doc | 0 MA25 | 0 TEST | 1 BATT_FAULT BOOT_SEL0 | 0 RESET# 83 ...
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Implementation Information This chapter summarizes some information about the implementation of the JTAG-Booster and describes some restrictions. The JTAG-Booster currently uses Boundary Scan to perform Flash programming. The XScale Onchip debugger is not used. The software assumes the following ...
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IXP425 signal 8 Bit Flash EX_CS0#..EX_CS1# CS# EX_CS2#..EX_CS3# EX_CS4#..EX_CS5# EX_CS6#..EX_CS7# EX_RD# OE# EX_WR# WE# EX_ADDR0 A0 EX_ADDR1 A1 EX_ADDR2..23 A2..23 EX_DATA0..7 D0..7 EX_DATA0..15 - EX_DATA0..31 - 1.) All other signals are hold static during flash programming. The state of these ...
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Converter Program HEX2BIN.EXE Since the JTAG-Booster software is not able to handle Intel-HEX or Motorola S- Record files, an separate converter tool is delivered with this product package. Five types of HEX formats can be converted to BIN file: ...
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Please Note: "CODE segment start address" is interpreted as a Intel x86 architecture segment address: You have to specify a start address of 10000 to start the conversion at 1 MByte. This converter is a relatively old DOS tool and ...
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Support for Windows NT, Windows 2000 and Windows XP A configured run time version of the "Kithara DOS Enabler, Version 6.x" is used to give support for some of our DOS based tools (like the JTAG-Booster) for Windows NT, ...
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... Now you can install the Kithara 6.x as described above. 5.4. De-Installation version 5.x/6.x: For deinstallation of the runtime version of the "Kithara DOS-Enabler Version 5.x/6.x": use: Settings - Control-Panel - Add/Remove Programs and remove the “FS FORTH-SYSTEME WinNT Support” and/or “WinNT Support for JTAG-Booster and FLASH166” Reboot your PC JTAG_XScaleb.doc 89 ...