CA3059

Manufacturer Part NumberCA3059
DescriptionZERO VOLTAGE CROSSING SWITCH
ManufacturerIntersil
CA3059 datasheet
 


Specifications of CA3059

Rohs StatusRoHS non-compliant  
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The circuit shown in Figure 19 forms a pulse of gate current
and can supply high peak drive to power triacs with low aver-
age current drain on the internal supply. The gate pulse will
always last just long enough to latch the thyristor so that
there is no problem with delaying the pulse to an optimum
time. As in other circuits of this type, RFI results if the load is
not suitable inductive because the zero crossing detector is
disabled and initial turn on occurs at random.
The gate pulse forms because the voltage at point A when
the thyristor is on is less than 1.3V; therefore, the output of
the zero-voltage switch is inhibited, as described above.
The resistor divider R
and R
should be selected to assure
1
2
this condition. When the triac is on, the voltage at point A is
approximately one third of the instantaneous on state
voltage (V
) of the thyristor. For most thyristors, V
T
less than 2V, and the divider shown is a conservative one.
When the load current passes through zero, the triac
commutates and turns off. Because the circuit is still being
driven by the line voltage, the current in the load attempts to
reverse, and voltage increases rapidly across the “turned-
off” triac. When this voltage exceeds 4V, one portion of the
CA3086 conducts and removes the inhibit signal to permit
application of gate drive. Turning the triac on causes the
voltage across it to drop and thus ends the gate pulse. If the
latching current has not been attained, another gate pulse
forms, but no discontinuity in the load current occurs.
5K
4W
5
9
R
P
10
11
2
120V
AC
ZVS
50-60Hz
13
1
39K
8
7
+
12
R
NTC
100/12V
SENSOR
14
11
5
CA3086
Q
4
Q
Q
5
13
12
10
4
3
FIGURE 19. USE OF THE CA3059 TOGETHER WITH 3086 FOR
SWITCHING INDUCTIVE LOADS
Application Note 6182
120V
AC
60Hz
100 F
+
15V
DC
-
(max) is
T
Provision of Negative Gate Current
Triacs trigger with optimum sensitivity when the polarity of
the gate voltage and the voltage at the main terminal 2 are
similar (I+ and II- modes). Sensitivity is degraded when the
polarities are opposite (I- and III+ modes). Although Intersil
triacs are designed and specified to have the same
sensitivity in both I- and III+ modes, some other types have
very poor sensitivity in the III+ condition. Because the
zero-voltage switch supplies positive gate pulses, it may
not directly drive some high current triacs of these other
types.
INDUCTIVE
LOAD
The circuit shown in Figure 20A. uses the negative going
voltage at terminal 3 of the zero-voltage switch to supply a
negative gate pulse through a capacitor. The curve in Figure
MT
2
20B. shows the approximate peak gate current as a function
of gate voltage V
4
MT
1
G
3
R
1
8
20K
1W
A
9
Q
3
2
R
2
10K
6
7
FIGURE 20. USE OF THE CA3059 TO PROVIDE NEGATIVE
10
R
L
50 F
5
6
1
3
10V
2
R
P
14
4
13
CA3059
8
V
S
NTC
7
SENSOR
9
10
11
12
V
R
. Pulse width is approximately 80 s.
G
FIGURE 20A.
40
30
20
10
0
0
-1
-2
-3
GATE VOLTAGE (V
) (V)
G
FIGURE 20B.
MT
2
-
MT
1
G