CAP CERM 2.2UF 6.3V X7R 0612 20%

W3L16C225MAT1A

Manufacturer Part NumberW3L16C225MAT1A
DescriptionCAP CERM 2.2UF 6.3V X7R 0612 20%
ManufacturerAVX Corporation
SeriesW3L
W3L16C225MAT1A datasheet
 


Specifications of W3L16C225MAT1A

Capacitance2.2µFTolerance±20%
Package / Case1206 (3216 Metric) Wide, 0612 (1632 Metric)Voltage - Rated6.3V
Temperature CoefficientX7RMounting TypeSurface Mount, MLCC
Operating Temperature-55°C ~ 125°CFeaturesLow ESL, Multi-Terminal
ApplicationsGeneral PurposeSize / Dimension0.126" L x 0.063" W (3.20mm x 1.60mm)
Thickness0.95mm MaxVoltage Rating6.3 Volts
Operating Temperature Range- 55 C to + 125 CTemperature Coefficient / CodeX7R
ProductLow Inductance MLCCsDimensions0.063 in W x 0.126 in L x 0.95 mm H
Dissipation Factor Df6.5Termination StyleSMD/SMT
Capacitance Tolerance± 20%Capacitor Case Style0612
Capacitor MountingSMDRohs CompliantYes
Lead Free Status / RoHS StatusLead free / RoHS CompliantRatings-
Lead Spacing-Other names478-4940-2
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Low Inductance Capacitors
Introduction
The signal integrity characteristics of a Power Delivery
Network (PDN) are becoming critical aspects of board level
and semiconductor package designs due to higher operating
frequencies, larger power demands, and the ever shrinking
lower and upper voltage limits around low operating voltages.
These power system challenges are coming from mainstream
designs with operating frequencies of 300MHz or greater,
modest ICs with power demand of 15 watts or more, and
operating voltages below 3 volts.
The classic PDN topology is comprised of a series of
capacitor stages. Figure 1 is an example of this architecture
with multiple capacitor stages.
An ideal capacitor can transfer all its stored energy to a load
instantly.
A real capacitor has parasitics that prevent
instantaneous transfer of a capacitor’s stored energy. The
true nature of a capacitor can be modeled as an RLC
equivalent circuit. For most simulation purposes, it is possible
to model the characteristics of a real capacitor with one
Slowest Capacitors
VR
Figure 1 Classic Power Delivery Network (PDN) Architecture
LOW INDUCTANCE CHIP CAPACITORS
The key physical characteristic determining equivalent series
inductance (ESL) of a capacitor is the size of the current loop
it creates. The smaller the current loop, the lower the ESL. A
standard surface mount MLCC is rectangular in shape with
electrical terminations on its shorter sides. A Low Inductance
Chip Capacitor (LICC) sometimes referred to as Reverse
Geometry Capacitor (RGC) has its terminations on the longer
side of its rectangular shape.
When the distance between terminations is reduced, the size
of the current loop is reduced. Since the size of the current
loop is the primary driver of inductance, an 0306 with a
smaller current loop has significantly lower ESL then an 0603.
The reduction in ESL varies by EIA size, however, ESL is
typically reduced 60% or more with an LICC versus a
standard MLCC.
capacitor, one resistor, and one inductor. The RLC values in
this model are commonly referred to as equivalent series
capacitance (ESC), equivalent series resistance (ESR), and
equivalent series inductance (ESL).
The ESL of a capacitor determines the speed of energy
transfer to a load. The lower the ESL of a capacitor, the faster
that energy can be transferred to a load. Historically, there
has been a tradeoff between energy storage (capacitance)
and inductance (speed of energy delivery). Low ESL devices
typically have low capacitance. Likewise, higher capacitance
devices typically have higher ESLs. This tradeoff between
ESL (speed of energy delivery) and capacitance (energy
storage) drives the PDN design topology that places the
fastest low ESL capacitors as close to the load as possible.
Low Inductance MLCCs are found on semiconductor
packages and on boards as close as possible to the load.
Semiconductor Product
Bulk
Board-Level
Package-Level
Low Inductance Decoupling Capacitors
INTERDIGITATED CAPACITORS
The size of a current loop has the greatest impact on the ESL
characteristics of a surface mount capacitor. There is a
secondary method for decreasing the ESL of a capacitor.
This secondary method uses adjacent opposing current
loops to reduce ESL. The InterDigitated Capacitor (IDC)
utilizes both primary and secondary methods of reducing
inductance.
between terminations to minimize the current loop size, then
further reduces inductance by creating adjacent opposing
current loops.
An IDC is one single capacitor with an internal structure that
has been optimized for low ESL. Similar to standard MLCC
versus LICCs, the reduction in ESL varies by EIA case size.
Typically, for the same EIA size, an IDC delivers an ESL that
is at least 80% lower than an MLCC.
Fastest Capacitors
Die-Level
The IDC architecture shrinks the distance
59

W3L16C225MAT1A Summary of contents

  • Page 1

    ... ESLs. This tradeoff between ESL (speed of energy delivery) and capacitance (energy storage) drives the PDN design topology that places the fastest low ESL capacitors as close to the load as possible. Low Inductance MLCCs are found on semiconductor packages and on boards as close as possible to the load. ...

  • Page 2

    ... LICA ® products are used in 99.999% uptime semiconductor package applications on both ceramic and organic substrates. The C4 solder ball termination option is the perfect compliment to flip-chip packaging technology. Mainframe class CPUs, ultimate performance multi-chip modules, and communications systems that must have the reliability of 5 9’ ...

  • Page 3

    ... CPU, GPU, ASIC, and ASSP devices produced on 0.13μ, 90nm, 65nm, and 45nm processes. IDC devices are used on both ceramic and organic package substrates. These low ESL surface mount capacitors can be placed on the bottom side or the top side of a package substrate. The low profile 0.55mm maximum height IDCs can easily be used on the bottom side of BGA packages or on the die side of packages under a heat spreader ...

  • Page 4

    ... IDC Low Inductance Capacitors (RoHS) 0612/0508 IDC (InterDigitated Capacitors) SIZE Thin 0508 mm 2.03 ± 0.20 Length (in.) (0.080 ± 0.008) mm 1.27 ± 0.20 Width (in.) (0.050 ± 0.008) Terminal mm 0.50 ± 0.05 Pitch (in.) (0.020 ± 0.002) mm 0.55 MAX. Thickness (in.) (0.022) MAX. WVDC 4 6.3 ...