74ACT18825 Fairchild Semiconductor, 74ACT18825 Datasheet

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74ACT18825

Manufacturer Part Number
74ACT18825
Description
18-Bit Buffer/Line Driver with 3-STATE Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
© 1999 Fairchild Semiconductor Corporation
74ACT18825SSC
74ACT18825MTD
74ACT18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
FACT , FACT Quiet Series
Order Number
Pin Names
OE
I
O
0
–I
0
–O
n
17
17
Output Enable Input (Active LOW)
Inputs
Outputs
Package Number
and GTO
MS56A
MTD56
Description
are trademarks of Fairchild Semiconductor Corporation.
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS0500292
Features
Connection Diagram
Broadside pinout allows for easy board layout
Separate control logic for each byte
Extra data width for wider address/data paths or buses
carrying parity
Outputs source/sink 24 mA
TTL-compatible inputs
Package Description
August 1999
Revised October 1999
www.fairchildsemi.com

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74ACT18825 Summary of contents

Page 1

... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT18825MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Functional Description The ACT18825 contains eighteen non-inverting buffers with 3-STATE standard outputs. The device is byte con- trolled with each byte functioning identically, but indepen- dently of the other. The control pins may be shorted together to obtain full 8-bit ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Output Diode Current ( 0. 0. Output ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH t Output Enable PZL t Time PZH t Output Disable PLZ t Time PHZ Note 4: Voltage Range 5.0 is 5.0V 0.5V. Capacitance Symbol Parameter C ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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