74aup1g74 NXP Semiconductors, 74aup1g74 Datasheet

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74aup1g74

Manufacturer Part Number
74aup1g74
Description
Low-power D-type Flip-flop With Set And Reset; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
CC
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 02 — 15 May 2007
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
.

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74aup1g74 Summary of contents

Page 1

... Rev. 02 — 15 May 2007 1. General description The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse ...

Page 2

... Table 1. Ordering information Type number Package Temperature range Name 74AUP1G74DC +125 C 74AUP1G74GT +125 C 74AUP1G74GM +125 C 4. Marking Table 2. Marking Type number 74AUP1G74DC 74AUP1G74GT 74AUP1G74GM 5. Functional diagram Fig 1. Logic symbol 74AUP1G74_2 Product data sheet Low-power D-type fl ...

Page 3

... 001aae323 Fig 6. Pin configuration SOT902-1 (XQFN8) Rev. 02 — 15 May 2007 74AUP1G74 C C 001aae087 74AUP1G74 terminal 1 index area Transparent top view © NXP B.V. 2007. All rights reserved 001aae324 ...

Page 4

... LOW) 1 asynchronous set input (active LOW) 8 supply voltage [ [ Rev. 02 — 15 May 2007 74AUP1G74 Output Output Q Q n+1 n © NXP B.V. 2007. All rights reserved ...

Page 5

... Active mode Power-down mode 0 3 Conditions Rev. 02 — 15 May 2007 74AUP1G74 Min Max 0.5 +4 [1] 0.5 +4 [1] 0 +150 [2] - 250 Min Max 0.8 3.6 0 3.6 ...

Page 6

... GND GND Rev. 02 — 15 May 2007 74AUP1G74 Min Typ Max ...

Page 7

... V 0 3.3 V; per pin Rev. 02 — 15 May 2007 74AUP1G74 Min Typ Max ...

Page 8

... 3 0 GND 3.3 V; per pin CC or GND. CC Rev. 02 — 15 May 2007 74AUP1G74 Min Typ Max ...

Page 9

... Figure 1 1 1. 2 3.6 V 1.8 CC Figure Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max ( 6.7 14.0 2.6 14.2 4.5 7.6 2.3 8.3 3.5 5.7 1.7 6.5 2.6 3.8 1.4 4.4 2.2 3.1 1.2 3.4 19 5.6 11 ...

Page 10

... Figure 1 1 1. 2 3.6 V 2.0 CC Figure Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max ( 7.5 15.8 2.9 16.1 5.1 8.7 2.4 9.4 4.1 6.5 2.2 7.2 3.2 4.6 1.8 5.3 2.8 3.8 1.6 4.1 23 6.5 12 ...

Page 11

... Figure 1 1 1. 2 3.6 V 2.4 CC Figure Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max ( 8.3 17.6 3.3 17.8 5.6 9.5 2.8 10.5 4.6 7.2 2.5 8.1 3.6 5.2 2.2 5.8 3.2 4.4 2.0 4.9 26 7.3 14 ...

Page 12

... Figure 1 1 1. 2 3.6 V 3.3 CC Figure Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max ( 10.6 22.5 4.0 23.0 7.2 12.0 3.7 13.3 5.8 9.2 3.4 10.4 4.7 6.6 3.0 7.3 4.3 5.8 2.8 6.8 37 9.5 19 ...

Page 13

... Figure Figure Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max ( 0.6 - 1.2 - 0.3 - 0.6 - 0.4 - 0.5 - 0.2 - 0.4 - 0.3 - 0 ...

Page 14

... where Rev. 02 — 15 May 2007 74AUP1G74 Figure +125 C [1] Max Min Max (85 C) 2.1 - 2.7 - 1.1 - 1.5 - 0.9 - 1.6 - 0.6 - 1.7 - 0.6 - 1.9 - 4.2 - 11.3 - 2.3 - 6.2 - 1.8 - 4 ...

Page 15

... GND PHL PLH Table 10. Input 0 Rev. 02 — 15 May 2007 74AUP1G74 PLH t PHL 001aae365 3 © NXP B.V. 2007. All rights reserved ...

Page 16

... GND t PLH PHL Table 11. Input 0 Rev. 02 — 15 May 2007 74AUP1G74 rec t rec PHL t PLH 001aae366 3 © NXP B.V. 2007. All rights reserved ...

Page 17

... Low-power D-type flip-flop with set and reset; positive-edge trigger PULSE DUT GENERATOR for measuring propagation delays, setup and hold times and pulse width R L Rev. 02 — 15 May 2007 74AUP1G74 V EXT 001aac521 of the pulse generator EXT t ...

Page 18

... Low-power D-type flip-flop with set and reset; positive-edge trigger 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 02 — 15 May 2007 74AUP1G74 detail 3.2 0.40 0.21 0.4 0.2 0.13 0.15 0.19 3.0 EUROPEAN PROJECTION SOT765 ...

Page 19

... Low-power D-type flip-flop with set and reset; positive-edge trigger scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 02 — 15 May 2007 74AUP1G74 4 ( EUROPEAN PROJECTION © NXP B.V. 2007. All rights reserved. SOT833-1 ISSUE DATE 04-07-22 04-11- ...

Page 20

... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 02 — 15 May 2007 74AUP1G74 detail 0.05 0.05 0.05 EUROPEAN PROJECTION SOT902 ISSUE DATE 05-11-16 05-11-25 © NXP B.V. 2007. All rights reserved ...

Page 21

... Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger Data sheet status Change notice Product data sheet - characteristics”: ) values. pd Product data sheet - Rev. 02 — 15 May 2007 74AUP1G74 Supersedes 74AUP1G74_1 - © NXP B.V. 2007. All rights reserved ...

Page 22

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 15 May 2007 74AUP1G74 © NXP B.V. 2007. All rights reserved ...

Page 23

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1G74 All rights reserved. Date of release: 15 May 2007 Document identifier: 74AUP1G74_2 ...

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