74aup1t97 NXP Semiconductors, 74aup1t97 Datasheet

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74aup1t97

Manufacturer Part Number
74aup1t97
Description
74aup1t97 Low-power Configurable Gate With Voltage-level Translator
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74aup1t97GF
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74aup1t97GF+132
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
V
This device ensures a very low static and dynamic power consumption across the entire
V
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
CC
74AUP1T97
Low-power configurable gate with voltage-level translator
Rev. 01 — 25 October 2007
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
or GND.
range from 2.3 V to 3.6 V.
OFF
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range.
CC
= 1.5 A (maximum)
CC
Product data sheet
OFF
.

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74aup1t97 Summary of contents

Page 1

... This device ensures a very low static and dynamic power consumption across the entire V range from 2 3 The 74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3 2.3 V. This device is fully specifi ...

Page 2

... C to +125 C 74AUP1T97GF +125 C 4. Marking Table 2. Marking Type number 74AUP1T97GW 74AUP1T97GM 74AUP1T97GF 5. Functional diagram Fig 1. Logic symbol 74AUP1T97_1 Product data sheet Low-power configurable gate with voltage-level translator Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package; no leads; ...

Page 3

... Description data input ground (0 V) data input data output supply voltage data input Rev. 01 — 25 October 2007 74AUP1T97 74AUP1T97 GND 001aag502 Transparent top view Fig 4. Pin configuration SOT891 (XSON6) Output ...

Page 4

... Fig 6. 2-input AND gate 001aae004 Fig 8. 2-input NOR gate with input B inverted 001aae006 Fig 10. Inverter Rev. 01 — 25 October 2007 74AUP1T97 001aae003 001aae005 ...

Page 5

... < Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode; V Rev. 01 — 25 October 2007 74AUP1T97 Min Max 0.5 +4 [1] 0.5 +4 [1] 0.5 +4 ...

Page 6

... GND GND Rev. 01 — 25 October 2007 74AUP1T97 Min Typ Max 0.60 - 1.10 0.75 - 1.16 0.35 - 0.60 0.50 - 0.85 0.23 - 0.60 0.25 - 0. 2.6 - ...

Page 7

... 2 3 2 3 2 4 GND Rev. 01 — 25 October 2007 74AUP1T97 Min Typ Max ...

Page 8

... 2 2 3.2 L [2] Figure 2.9 L [2] Figure 3.6 L Rev. 01 — 25 October 2007 74AUP1T97 Min Typ = [ [ 13 +125 C [1] Typ Max Min Max (85 C) 3.5 5.5 0.5 6.8 4.1 6.3 1.0 7.9 4.6 6.9 1.0 8.7 5.8 8.4 1.5 10.8 3 ...

Page 9

... 2 2 3.2 L [2] Figure 2.9 L [3] = GND where Rev. 01 — 25 October 2007 74AUP1T97 13 +125 C [1] Typ Max Min Max (85 C) 2.8 4.2 0.5 5.3 3.4 5.0 1.0 6.1 3.8 5.6 1.0 6.8 5.0 7.1 1.5 8.5 2.7 4.2 0.5 4.7 3.3 5.0 1.0 5.7 3.8 5.6 1.0 6.2 4.9 7.1 1.5 7.8 3 ...

Page 10

... GND t PHL output PLH output Table 10. Input Rev. 01 — 25 October 2007 74AUP1T97 PLH PHL V M 001aab593 1. 3.6 V 3.0 ns © NXP B.V. 2007. All rights reserved ...

Page 11

... V EXT [ PLH open = for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 25 October 2007 74AUP1T97 V EXT PHL PZH PHZ PZL GND 2 © NXP B.V. 2007. All rights reserved. ...

Page 12

... scale 2.2 1.35 2.2 1.3 0.65 1.8 1.15 2.0 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 25 October 2007 74AUP1T97 detail 0.45 0.25 0.2 0.2 0.1 0.15 0.15 EUROPEAN PROJECTION SOT363 ISSUE DATE 04-11-08 06-03-16 © NXP B.V. 2007. All rights reserved. ...

Page 13

... Low-power configurable gate with voltage-level translator scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 25 October 2007 74AUP1T97 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2007. All rights reserved ...

Page 14

... Low-power configurable gate with voltage-level translator scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 25 October 2007 74AUP1T97 SOT891 4 ( EUROPEAN ISSUE DATE PROJECTION 05-04-06 07-05-15 © NXP B.V. 2007. All rights reserved ...

Page 15

... Revision history Table 13. Revision history Document ID Release date 74AUP1T97_1 20071025 74AUP1T97_1 Product data sheet Low-power configurable gate with voltage-level translator Data sheet status Product data sheet Rev. 01 — 25 October 2007 74AUP1T97 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 25 October 2007 74AUP1T97 © NXP B.V. 2007. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1T97 All rights reserved. Date of release: 25 October 2007 Document identifier: 74AUP1T97_1 ...

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