74AUP2G80 Philips Semiconductors, 74AUP2G80 Datasheet

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74AUP2G80

Manufacturer Part Number
74AUP2G80
Description
Low-power dual D-type flip-flop
Manufacturer
Philips Semiconductors
Datasheet

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1. General description
2. Features
The 74AUP2G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
The 74AUP2G80 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock
transition for predictable operation.
CC
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 01 — 25 August 2006
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114-D Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
.

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74AUP2G80 Summary of contents

Page 1

... OFF the device when it is powered down. The 74AUP2G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation ...

Page 2

... Type number Package Temperature range Name 74AUP2G80DC +125 C 74AUP2G80GT +125 C 74AUP2G80GM +125 C 4. Marking Table 2. Marking Type number 74AUP2G80DC 74AUP2G80GT 74AUP2G80GM 5. Functional diagram 1D 2 1CP 2CP 5 001aaf306 Fig 1. Logic symbol CP D Fig 3. Logic diagram (one flip-flop) ...

Page 3

... Rev. 01 — 25 August 2006 74AUP2G80 2CP 74AUP2G80 terminal 1 index area 2CP 3 Transparent top view © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 7 1CP 001aaf310 ...

Page 4

... Active mode and Power-down mode +125 C amb derates linearly with 8.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 01 — 25 August 2006 74AUP2G80 Output Min Max Unit 0.5 +4 [1] 0.5 +4 ...

Page 5

... 3 0 GND GND GND Rev. 01 — 25 August 2006 74AUP2G80 Min Typ Max 0 0.75 V ...

Page 6

... GND Rev. 01 — 25 August 2006 74AUP2G80 Min Typ Max 0 ...

Page 7

... GND GND. CC Rev. 01 — 25 August 2006 74AUP2G80 Min Typ Max 0 ...

Page 8

... Low-power dual D-type flip-flop; positive-edge trigger Figure 25 C Min Typ [2] Figure 7 - 20.9 2.9 1.9 1.7 1.4 1.2 Figure 203 - 347 - 435 - 550 - 619 [2] Figure 7 - 24.6 3.3 2.6 2.3 1.9 1.8 Figure 192 - 324 - 421 - 486 - 550 Rev. 01 — 25 August 2006 74AUP2G80 +125 C [1] Max Min Max (85 C) (85 C) (125 6.0 12.9 2.6 14.3 4.2 7.6 2.0 8.9 3.4 5.9 1.6 7.0 2.6 4.3 1.2 5.6 2.2 3.6 1.0 4 170 - - 310 - - 400 - - 490 ...

Page 9

... Figure 25 C Min Typ [2] Figure 7 - 28.2 3.0 3.0 2.6 2.2 1.9 Figure 181 - 301 - 407 - 422 - 481 [2] Figure 7 - 38.8 4.9 4.0 3.5 3.1 2.9 Figure 128 - 206 - 262 - 269 - 309 Figure Rev. 01 — 25 August 2006 74AUP2G80 +125 C [1] Max Min Max (85 C) (85 C) (125 7.6 16.7 3.4 18.6 5.3 9.8 2.6 11.5 4.4 7.6 2.3 9.1 3.5 5.7 2.0 6.9 3.1 5.0 1.8 5 120 - - 190 - - 240 - - 300 - - 320 - - - - 9 ...

Page 10

... Low-power dual D-type flip-flop; positive-edge trigger …continued Figure 25 C Min Typ Figure 8 - 1.7 - 0.3 - 0.2 - 0.2 - 0.3 - 0.3 Figure 5.2 - 1.0 - 0.8 - 0.6 - 0.5 - 0.5 [3] = GND 1.8 - 1.8 - 1.9 - 2.0 - 2 where Rev. 01 — 25 August 2006 74AUP2G80 +125 C [1] Max Min Max Min (85 C) (85 C) (125 0 ...

Page 11

... GND PLH Table 9. Input 0 Rev. 01 — 25 August 2006 74AUP2G80 PHL V M 001aaf311 su(H) t PHL 001aaf312 3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 12

... Low-power dual D-type flip-flop; positive-edge trigger PULSE DUT GENERATOR for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 25 August 2006 74AUP2G80 V EXT 001aac521 of the pulse generator EXT t ...

Page 13

... 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 01 — 25 August 2006 74AUP2G80 detail 3.2 0.40 0.21 0.4 0.2 0.13 0.15 0.19 3.0 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...

Page 14

... Low-power dual D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 01 — 25 August 2006 74AUP2G80 4 ( EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. SOT833-1 ISSUE DATE 04-07-22 04-11- ...

Page 15

... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 01 — 25 August 2006 74AUP2G80 detail 0.05 0.05 0.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. SOT902 ISSUE DATE 05-11-16 05-11- ...

Page 16

... Revision history Document ID Release date 74AUP2G80_1 20060825 74AUP2G80_1 Product data sheet Low-power dual D-type flip-flop; positive-edge trigger Data sheet status Change notice Product data sheet - Rev. 01 — 25 August 2006 74AUP2G80 Supersedes - © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 17

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 01 — 25 August 2006 74AUP2G80 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 18

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. 74AUP2G80 All rights reserved. Date of release: 25 August 2006 Document identifier: 74AUP2G80_1 ...

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