74F675A Fairchild, 74F675A Datasheet
74F675A
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74F675A Summary of contents
Page 1
... Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contains a 16-bit serial in/serial out shift reg- ister and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register ...
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... Shift Right Parallel Load, No Shifting Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com U.L. Description HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 The storage register is in the Hold mode when either CS or R/W is HIGH ...
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... Recognized as a LOW Signal Min Min Min Max V 2.7V IN Max V 7.0V IN Max V V OUT 0.0 All Other Pins Grounded V 150 mV IOD 0.0 All Other Pins Grounded Max V 0.5V IN Max V 0V OUT Max V HIGH O Max V LOW O www.fairchildsemi.com ...
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... CS to SHCP H t (H) SHCP Pulse Width W t (L) HIGH or LOW W t (H) STCP Pulse Width W t (L) HIGH or LOW W t (L) SHCP to STCP S t (H) SHCP to STCP H www.fairchildsemi.com 5. Min Typ Max Min 100 130 85 3.0 8.0 10 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number M24B Package Number N24A 5 www.fairchildsemi.com ...
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...