74F825 Fairchild, 74F825 Datasheet
74F825
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74F825 Summary of contents
Page 1
... D-Type Flip-Flop General Description The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming sys- tems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. ...
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... When the OE is HIGH, the outputs go to the high impedance state. Opera- tion of the OE input does not affect the state of the flip- flops. The 74F825 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW the outputs are LOW ...
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... Min Max V 2.7V IN Max V 7.0V IN Max V V OUT 0.0 All Other Pins Grounded V 150 mV IOD 0.0 All Other Pins Grounded Max V 0.5V IN Max V 2.7V OUT Max V 0.5V OUT Max V 0V OUT 0.0V V 5.25V OUT Max V HIGH Z O www.fairchildsemi.com ...
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... Hold Time, HIGH or LOW (H) CP Pulse Width W t (L) HIGH or LOW W t (L) CLR Pulse Width, LOW W t CLR Recovery Time REC www.fairchildsemi.com 125 5. Min Typ Max Min ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com ...
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...