74lcx16652 Fairchild Semiconductor, 74lcx16652 Datasheet

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74lcx16652

Manufacturer Part Number
74lcx16652
Description
74lcx16652 Low Voltage Transceiver/register With 5v Tolerant Inputs And Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
© 2001 Fairchild Semiconductor Corporation
74LCX16652MEA
74LCX16652MTD
74LCX16652
Low Voltage Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX16652 contains sixteen non-inverting bidirectional
bus transceivers with 3-STATE outputs providing multi-
plexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Output Enable pins (OEAB, OEBA)
are provided to control the transceiver function (see Func-
tional Description).
The LCX16652 is designed for low-voltage (2.5V or 3.3V)
V
environment.
The LCX16652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with capability of interfacing to a 5V signal
Package Number
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS012005
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
value or the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
A
B
CPAB
SAB
OEAB
0
0
5V tolerant inputs and outputs
2.3V–3.6V V
5.7 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Pin Names
–A
–B
24 mA output drive (V
Human body model
Machine model
n
15
15
, SBA
n
Package Description
n
, CPBA
, OEBA
PD
n
max (V
CC
CC
n
n
and OE tied to GND through a resistor: the minimum
specifications provided
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Inputs
CC
200V
3.3V), 20 A I
CC
2000V
3.0V)
February 1994
Revised April 2001
Description
CC
www.fairchildsemi.com
max

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74lcx16652 Summary of contents

Page 1

... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagram Truth Table (Note 2) Inputs OEAB OEBA CPAB CPBA SAB ...

Page 3

... register or both. The select (SAB , SBA ) controls can multiplex stored and n n real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the 74LCX16652. Real-Time Transfer Bus B to Bus A OEAB OEBA CPAB CPBA SAB 1 1 ...

Page 4

Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 ...

Page 5

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 6

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL t ...

Page 7

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...

Page 8

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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