74LCX38M Fairchild Semiconductor, 74LCX38M Datasheet

IC GATE NAND QUAD 2IN OD 14SOIC

74LCX38M

Manufacturer Part Number
74LCX38M
Description
IC GATE NAND QUAD 2IN OD 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX38M

Logic Type
NAND Gate with Open Drain
Number Of Inputs
2
Number Of Circuits
4
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
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Manufacturer:
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© 2005 Fairchild Semiconductor Corporation
74LCX38M
74LCX38MX_NL
(Note 1)
74LCX38SJ
74LCX38MTC
74LCX38MTCX_NL
(Note 1)
74LCX38
Low Voltage Quad 2-Input NAND Gate (Open Drain)
with 5V Tolerant Inputs
General Description
The LCX38 contains four 2-input open drain NAND gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
The 74LCX38 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Pin Descriptions
Order Number
Package
Number
MTC14
MTC14
M14A
M14A
M14D
IEEE/IEC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
A
O
n
n
, B
n
Pin Names
DS012574
Inputs
Outputs
Features
Connection Diagram
5V tolerant inputs
2.3V to 3.6V V
5.0 ns t
Power down high impedance inputs and outputs
24 mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Description
Human body model
Machine model
Package Description
PD
max (V
CC
CC
specifications provided
!
150V
CC
!
3.3V), 10
2000V
3.0V)
October 1995
Revised February 2005
P
A I
CC
www.fairchildsemi.com
max

Related parts for 74LCX38M

74LCX38M Summary of contents

Page 1

... M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX38MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX38MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink Current ( ...

Page 3

AC Electrical Characteristics Symbol Parameter t Propagation Delay Time PZL t PLZ t Output to Output Skew OSHL t (Note 5) OSLH Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for ...

Page 4

AC Loading and Waveforms (C t PZL 3-STATE Output Low Enable and Disable Times for Logic (Input Pulse Characteristics 1MHz, t Symbol www.fairchildsemi.com Generic for LCX Family FIGURE 1. AC ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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