74LVQ241SJ Fairchild Semiconductor, 74LVQ241SJ Datasheet

IC BUFF/DVR TRI-ST DUAL 20SOP

74LVQ241SJ

Manufacturer Part Number
74LVQ241SJ
Description
IC BUFF/DVR TRI-ST DUAL 20SOP
Manufacturer
Fairchild Semiconductor
Series
74LVQr
Datasheet

Specifications of 74LVQ241SJ

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
4
Current - Output High, Low
12mA, 12mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOP
Logic Family
LVQ
Number Of Channels Per Chip
8
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 12 mA
Low Level Output Current
12 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
8 / 8
Output Type
3-State
Propagation Delay Time
12.7 ns at 2.7 V, 9 ns at 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74LVQ241SC
74LVQ241SJ
74LVQ241QSC
74LVQ241
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVQ241 is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus oriented transmitter or receiver which provides
improved PC board density.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
Pin Descriptions
Order Number
OE
I
O
0
–I
0
Pin Names
1
–O
7
, OE
7
2
3-STATE Output Enable Inputs
Inputs
Outputs
Package Number
IEEE/IEC
MQA20
M20B
M20D
Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
DS011355
Features
Connection Diagram
Truth Tables
H
L
Ideal for low power/low noise 3.3V applications
Implements patented EMI reduction circuitry
Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-
ages
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Improved latch-up immunity
Guaranteed incident wave switching into 75
4 kV minimum ESD immunity
LOW Voltage Level Z
HIGH Voltage Level X
OE
OE
H
H
H
L
L
L
Package Description
1
2
Inputs
Inputs
I
I
H
X
X
H
n
L
n
L
High Impedance
Immaterial
February 1992
Revised June 2001
(Pins 12, 14, 16, 18)
(Pins 3, 5, 7, 9)
www.fairchildsemi.com
Outputs
Outputs
H
H
L
Z
Z
L

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74LVQ241SJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74LVQ241SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ241SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ241QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Device also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 3

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH t Output Enable Time PZL t PZH t Output Disable Time PHZ t PLZ t Output to Output OSHL t Skew Data to Output (Note 9) ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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