74vhc175 Fairchild Semiconductor, 74vhc175 Datasheet

74vhc175

Manufacturer Part Number

74vhc175

Description

Quad D-type Flip-flop

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VHC175.pdf (7 pages)

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74VHC175M

74VHC175SJ

74VHC175MTC

74VHC175N

74VHC175

Quad D-Type Flip-Flop

General Description

The VHC175 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It achieves

the high-speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation.

The VHC175 is a high-speed quad D-type flip-flop. The

device is useful for general flip-flop requirements where

clock and clear inputs are common. The information on the

D inputs is stored during the LOW-to-HIGH clock transition.

Both true and complemented outputs of each flip-flop are

provided. A Master Reset input resets all flip-flops, inde-

pendent of the Clock or D inputs, when LOW.

An input protection circuit insures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Logic Symbols

Order Number

Package Number

MTC16

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS011637.prf

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery backup. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

Pin Descriptions

High Speed: f

Low power dissipation: I

High noise immunity: V

Power down protection is provided on all inputs

Low noise: V

Pin and function compatible with 74HC175

Package Description

Pin Names

–D

–Q

OLP

MAX

0.8V (max)

210 MHz (typ) at V

IEEE/IEC

NIH

Data Inputs

Clock Pulse Input

Master Reset Input

True Outputs

Complement Outputs

August 1993

Revised April 1999

4 A (max) at T

Description

NIL

28% V

www.fairchildsemi.com

(min)

25 C

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74vhc175 Summary of contents

Page 1

... MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Functional Description The VHC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( OUT Input Diode Current ( Output Diode Current ( Output Current (I ) ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) f Maximum Clock 3.3 0.3 MAX Frequency 5.0 0.5 t Propagation Delay 3.3 0.3 PLH t Time ( PHL n n 5.0 0.5 t Propagation Delay Time ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16A Package Number M16D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC16 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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