74vhc4046 National Semiconductor Corporation, 74vhc4046 Datasheet

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74vhc4046

Manufacturer Part Number
74vhc4046
Description
Cmos Phase Lock Loop
Manufacturer
National Semiconductor Corporation
Datasheet

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C 1995 National Semiconductor Corporation
74VHC4046
CMOS Phase Lock Loop
General Description
The 74VHC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high fre-
quency operation both in the phase comparator and VCO
sections This device contains a low power linear voltage
controlled oscillator (VCO) a source follower and three
phase comparators The three phase comparators have a
common signal input and a common comparator input The
signal input has a self biasing amplifier allowing signals to
be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard input
logic levels This device is similar to the CD4046 except that
the Zener diode of the metal gate CMOS device has been
replaced with a third phase comparator
Phase Comparator I is an exclusive OR (XOR) gate It pro-
vides a digital error signal that maintains a 90 phase shift
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms) This phase detector is
more susceptible to locking onto harmonics of the input fre-
quency than phase comparator I but provides better noise
rejection
Phase comparator III is an SR flip-flop gate It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance
Phase comparator II is an edge sensitive digital sequential
network Two signal outputs are provided a comparator out-
put and a phase pulse output The comparator output is a
TRI-STATE
VCO output signal to the input signal with 0 phase shift be-
tween them This comparator is more susceptible to noise
throwing the loop out of lock but is less likely to lock onto
harmonics than the other two comparators
TRI-STATE is a registered trademark of National Semiconductor Corporation
Note Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter ‘‘X’’ to the ordering code
output that provides a signal that locks the
74VHC4046M
74VHC4046N
Commercial
TL F 11675
M16A
N16E
Package
Number
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input This input is a very high impedance CMOS input
which also drives the source follower The VCO’s operating
frequency is set by three external components connected to
the C1A C1B R1 and R2 pins An inhibit pin is provided to
disable the VCO and the source follower providing a meth-
od of putting the IC in a low power state
The source follower is a MOS transistor whose gate is con-
nected to the VCO input and whose drain connects the De-
modulator output This output normally is used by tying a
resistor from pin 10 to ground and provides a means of
looking at the VCO input without loading down modifying the
characteristics of the PLL filter
Features
Y
Y
Y
Y
Y
Low dynamic power consumption
Maximum VCO operating frequency
(V
Fast comparator response time (V
VCO has high linearity and high temperature stability
Pin and function compatible with the 74HC4046
CC
Comparator I
Comparator II
Comparator III
e
4 5V)
16-Lead Molded JEDEC SOIC
16-Lead Molded DIP
Package Description
CC
RRD-B30M125 Printed in U S A
e
4 5V)
October 1995
(V
CC
12 MHz
e
25 ns
30 ns
25 ns
4 5V)

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74vhc4046 Summary of contents

Page 1

... CMOS Phase Lock Loop General Description The 74VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high fre- quency operation both in the phase comparator and VCO sections This device contains a low power linear voltage controlled oscillator (VCO) a source follower and three ...

Page 2

Block and Connection Diagrams Pin Assignment for SOIC and PDIP TL F 11675 – 11675 – 1 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( OUT Clamp Diode Current ( Output ...

Page 4

AC Electrical Characteristics Symbol Parameters AC Coupled C (series) e Input Sensitiv ity Signal Maximum Output r f Rise and Fall Time C Maximum Input IN Capacitance Phase Comparator Maximum Prop- PHL ...

Page 5

Typical Performance Characteristics Typical Center Frequency Typical Offset Frequency Typical Center Frequency 11675 – 3 Typical Offset Frequency ...

Page 6

Typical Performance Characteristics VHC4046 Typical VCO Power Dissipation Center Frequency VHC4046 VCO out CC VHC4046 VCO vs out e Temperature (Continued) VHC4046 Typical VCO Power Dissipation TL F 11675 ...

Page 7

Typical Performance Characteristics VHC4046 Typical Source Follower Power Dissipation vs RS VHC4046 Typical VCO Linearity vs R1 VCO WITHOUT OFFSET R2 (Continued) Typical 11675 – VHC4046 Typical VCO Linearity vs ...

Page 8

Comparator – Given f – Given – Use f with curve titled – Calculate f 0 center frequency equation f to determine R1 and C1 – Use f with ...

Page 9

Detailed Circuit Description the capacitor once the capacitor charges up to the thresh- old of the schmitt trigger the oscillator logic flips the capaci- tor over and causes the mirror to charge the opposite side of the capacitor The output ...

Page 10

Detailed Circuit Description Thus in normal operation V and ground voltage levels are CC fed to the loop filter This differs from some phase detectors which supply a current output to the loop filter and this should be considered in ...

Page 11

Detailed Circuit Description FIGURE 6 Logic Diagram for Phase Comparator II FIGURE 7 Typical Phase Comparator II Output Waveforms (Continued 11675 – 11675 – 23 ...

Page 12

Detailed Circuit Description means that the VCO’s frequency must be increased to bring its leading edge into proper phase alignment Thus the phase detector II output is set high This will cause the loop filter to charge up the VCO ...

Page 13

... The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows Physical Dimensions inches (millimeters) 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC Order Number 74VHC4046M NS Package Number M16A 11675 – 26 ...

Page 14

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Molded Dual-In-Line Package (N) Order Number 74VHC4046N NS Package Number N16E 2 A critical component is any component of a life ...

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