74vhc573 STMicroelectronics, 74vhc573 Datasheet

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74vhc573

Manufacturer Part Number
74vhc573
Description
Octal D-type Latch With 3 State Output Non Inverting
Manufacturer
STMicroelectronics
Datasheet

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74vhc573MTR
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DESCRIPTION
The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
CC
PLH
OH
NIH
CC
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 5.5V
2
= V
MOS technology.
t
PHL
OL
NIL
= 8 mA (MIN)
= 28% V
OLP
PD
= 5.0 ns (TYP.) at V
= 0.9V (MAX.)
CC
A
=25°C
(MIN.)
WITH 3 STATE OUTPUTS NON INVERTING
CC
= 5V
Table 1: Order Codes
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while (OE) is in high level, the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
OCTAL D-TYPE LATCH
SOP
SOP
74VHC573
Rev. 5
74VHC573MTR
74VHC573TTR
TSSOP
T & R
1/14

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74vhc573 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY LOW NOISE 0.9V (MAX.) OLP DESCRIPTION The 74VHC573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE) ...

Page 2

... Figure 2: Input Equivalent Circuit Table 3: Truth Table Don’t Care Z : High Impedance * : Q Outputs are Latched at the time when the LE input is taken low logic level. Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14 Table 2: Pin Description PIN N° ...

Page 3

... V Input Voltage I V Output Voltage O T Operating Temperature op Input Rise and Fall Time (note 1) (V dt/ from 30 Parameter Parameter = 3.3 0.3V 5.0 0.5V) CC 74VHC573 Value Unit -0.5 to +7.0 V -0.5 to +7 -65 to +150 °C 300 °C Value Unit ...

Page 4

... Table 6: DC Specifications Symbol Parameter V High Level Input IH Voltage 3 Low Level Input IL Voltage 3 High Level Output OH Voltage V Low Level Output OL Voltage I High Impedance OZ Output Leakage Current I Input Leakage I Current I Quiescent Supply CC Current 4/14 Test Condition (V) Min. 2.0 1.5 0.7V CC 5.5 2.0 5 ...

Page 5

... Max. Min. Max. Min. 7.6 11.9 1.0 14.0 1.0 10.1 15.4 1.0 17.5 1.0 5.0 7.7 1.0 9.0 1.0 6.5 9.7 1.0 11.0 1.0 7.0 11.0 1.0 13.0 1.0 9.5 14.5 1.0 16.5 1.0 4.5 6.8 1.0 8.0 1.0 6.0 8.8 1.0 10.0 1.0 7.3 11.5 1.0 13.5 1.0 9.8 15.0 1.0 17.0 1.0 5.2 7.7 1.0 9.0 1.0 6.7 9.7 1.0 11.0 1.0 10.7 14.5 1.0 16.5 1.0 6.7 9.7 1.0 11 1.0 5.0 5.0 5.0 5.0 3.5 3.5 3.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1 pHLn Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74VHC573 Unit Max. 14.0 17.5 ns 9.0 11.0 13.0 16.5 ns 8.0 10.0 13.5 ns 17.0 9.0 ns 11.0 16 5.0 ns 5.0 3.5 ns 3.5 1.5 ns 1.5 1.5 ns 1.0 Unit Max (per Latch 5/14 ...

Page 6

... Table 9: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low OLP Voltage Quiet V OLV Output (note 1, 2) Dynamic High V Voltage Input IHD (note 1, 3) Dynamic Low V Voltage Input ILD (note Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. ...

Page 7

... Figure 5: Waveform - Propagation Delays, LE Minimum Pulse Width Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 74VHC573 7/14 ...

Page 8

... Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 8/14 ...

Page 9

... MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd mm. TYP MAX. 2.65 0.093 0.30 0.004 0.51 0.013 0.32 0.009 13.00 0.496 7.6 0.291 1.27 10.65 0.394 0.75 0.010 1.27 0.016 8° 0.100 74VHC573 inch MIN. TYP. 0.050 0° 0016022D MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.419 0.030 0.050 8° 0.004 9/14 ...

Page 10

... DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0˚ PIN 1 IDENTIFICATION 1 10/14 TSSOP20 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 6.5 6.6 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.252 0.256 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 ...

Page 11

... Tape & Reel SO-20 MECHANICAL DATA DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 30.4 11 0.425 13.4 0.520 3.3 0.122 4.1 0.153 12.1 0.468 74VHC573 inch MIN. TYP. MAX. 12.992 0.519 1.197 0.433 0.528 0.130 0.161 0.476 11/14 ...

Page 12

... Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 12/14 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 0.067 4.1 0.153 12.1 0.468 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.276 0.280 0.075 0.161 0.476 ...

Page 13

... Table 10: Revision History Date Revision 12-Nov-2004 5 Description of Changes Order Codes Revision - pag. 1. 74VHC573 13/14 ...

Page 14

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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