82C55A Intersil Corporation, 82C55A Datasheet
82C55A
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82C55A Summary of contents
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... Copyright Description The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation ...
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... RESET: A high on this input clears the control register and all ports ( are set to the input mode with the “Bus Hold” circuitry turned on. I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus ...
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... Chip Select. A “low” on this input pin enables the communcation between the 82C55A and the CPU. (RD) Read. A “low” on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A. ...
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... Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 82C55A. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “ ...
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... BIT SET/RESET FLAG 0 = ACTIVE FIGURE 5. BIT SET/RESET FORMAT Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE fl ...
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... PC3 - PC0 8 PB7 - PB0 6 tHR tRA tDF tWD tWA tWB PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 B ...
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... PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 ...
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... A PA7 - PA0 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 PC3 - PC0 8 PB7 - PB0 B MODE 1 (PORT A) PA7-PA0 INTE PC4 A 1/0 PC5 PC6, PC7 1 = INPUT 0 = OUTPUT PC3 2 RD PC6, PC7 ...
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... WR input and reset by ACK input being low. ACK - Acknowledge Input). A “low” on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data, (See Note 1). ...
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... A) Bi-Directional Bus I/O Control Signal Definition (Figures 11, 12, 13, 14) INTR - (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. 82C55A tWOB tWIT tAK tWB FIGURE 9. MODE 1 (STROBED OUTPUT) ...
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... DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL FIGURE 13. MODE 2 (BI-DIRECTIONAL) 11 INTRA PC3 PA7-PA0 8 PC7 OBFA INTE PC6 ACKA 1 INTE STBA PC4 2 PC5 IBFA 3 PC2-PC0 I/O FIGURE 12. MODE 2 tAOB tAK tAD tKD tRIB DATA FROM DATA FROM 82C55A TO CPU OBF ...
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... PC2-PC0 1 = INPUT 0 = OUTPUT RD WR MODE 2 AND MODE 1 (OUTPUT) CONTROL WORD 82C55A MODE 2 AND MODE 0 (OUTPUT) PC3 INTRA PA7-PA0 8 OBFA PC7 CONTROL WORD ACKA PC6 PC4 STBA PC2-PC0 PC5 ...
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... Mode 0 or Mode 1 Selection) FIGURE 16. MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. 13 ...
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... REQUEST INTERRUPT REQUEST 82C55A Applications of the 82C55A The 82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system. It represents the optimum use of available pins and flexible enough to inter- face almost any I/O device without the need for additional external logic. ...
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... FULLY INTERRUPT REQUEST PC3 MODE 1 (INPUT) 82C55A MODE 0 (INPUT) FIGURE 20. KEYBOARD AND TERMINAL ADDRESS INTERFACE INTERRUPT REQUEST PC3 MODE 1 ANALOG (OUTPUT) OUTPUT 82C55A MODE 0 ANALOG (OUTPUT) INPUT FIGURE 22. BASIC CRT CONTROLLER INTERFACE 15 PA0 R0 PA1 R1 PA2 R2 FULLY PA3 R3 DECODED PA4 R4 KEYBOARD ...
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... MODE 0 PB4 DISC SELECT (OUTPUT) PB5 ENABLE CRC PB6 TEST PB7 BUSY LT FIGURE 23. BASIC FLOPPY DISC INTERFACE 82C55A INTERRUPT REQUEST AND DRIVE MODE 1 (INPUT) 82C55A MODE 0 (INPUT) MODE 0 (OUTPUT) FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE 16 PC3 PA0 R0 PA1 R1 PA2 R2 B LEVEL PA3 R3 ...
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... Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Operating Temperature Range C82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 I82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 M82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... C (M82C55A) (M82C55A-5 (I82C55A) (I82C55A-5); 82C55A TEST MIN MAX UNITS CONDITIONS 150 - ns - 120 300 - 100 - ns 100 ...
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... Timing Waveforms RD INPUT CS, A1, A0 D7-D0 WR D7-D0 tAW (7) CS, A1, A0 OUTPUT STB IBF INTR RD INPUT FROM PERIPHERAL 82C55A tRR (3) tIR (13) tAR (1) tRD (4) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) tDW (10) FIGURE 26. MODE 0 (BASIC OUTPUT) tST (16) tSIB (23) tSIT (26) tRIT (25) tPH (18) tPS (17) FIGURE 27. MODE 1 (STROBED INPUT) 19 tHR (14) ...
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... NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF MASK ACK WR) 82C55A tWOB (21) tAOB (22) tWIT (28) tAK (15) tWB (12) FIGURE 28. MODE 1 (STROBED OUTPUT) tWOB (21) tST (16) (NOTE) tSIB (23) tPS (17) tPH (18) DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL FIGURE 29. MODE 2 (BI-DIRECTIONAL) 20 tAIT (27) (NOTE) tAOB (22) tAK (15) tAD (19) tKD (20) tRIB (24) DATA FROM DATA FROM 82C55A TO CPU ...
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... Timing Waveforms (Continued) A0-A1, CS tAW (7) DATA BUS tDW (10) WR tWW (9) FIGURE 30. WRITE TIMING AC Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST R2 NOTE: Includes STRAY and JIG Capacitance Burn-In Circuits MD82C55A CERDIP GND 7 34 ...
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... CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 82C55A GLASSIVATION: Type: SiO 2 Thickness: 8k WORST CASE CURRENT DENSITY 82C55A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 22 Å Å A/cm WR RESET D0 D1 ...
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... B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 82C55A E40.6 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL A ...
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... D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line measured at seating plane -C- 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 82C55A N44.65 0.004 (0.10 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.025 (0.64) ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 82C55A F40.6 c1 LEAD FINISH MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A) 40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE BASE (c) ...
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... -E- 0.007 -H- - 82C55A J44.A MIL-STD-1835 CQCC1-N44 (C-5) 44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL MIN A 0.064 A1 0.054 B 0.033 B1 0.022 B2 0.072 REF 0.006 D 0.640 D1 0.500 BSC D2 0.250 BSC ...