a4935 Allegro MicroSystems, Inc., a4935 Datasheet
a4935
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a4935 Summary of contents
Page 1
... MOSFETs and is specifically designed for automotive applications. A unique charge pump regulator provides full (>10 V) gate drive for battery voltages down and allows the A4935 to operate with a reduced gate drive, down to 5 bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows DC (100% duty cycle) operation ...
Page 2
... THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance *Additional thermal information available on Allegro website. Automotive 3-Phase MOSFET Driver The A4935 is supplied in a 48-pin LQFP with exposed thermal pad, (suffix JP). This is a small footprint (81 mm lead (Pb) free with 100% matte tin leadframe plating. Packing Symbol ...
Page 3
... A4935 VBB Logic VDD Supply COAST PWMH PWML AHI Control ALO Logic BHI BLO CHI CLO CCEN RESET RDEAD Diagnostics and Protection ESF Short to Supply FF1 FF2 VDSTH Automotive 3-Phase MOSFET Driver Functional Block Diagram C P CP1 CP2 Charge Pump Regulator ...
Page 4
... A4935 ELECTRICAL CHARACTERISTICS valid at T Characteristics Supply and Reference Load Supply Voltage Functional Operating Range 1 Load Supply Quiescent Current Logic Supply Voltage Logic Supply Quiescent Current VREG Output Voltage Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit ...
Page 5
... A4935 ELECTRICAL CHARACTERISTICS (continued) valid at T unless noted otherwise Characteristics Dead Time 2 Logic Inputs and Outputs FF1 and FF2 Fault Output FF1 and FF2 Fault Output Leakage Current RDEAD Input Low Voltage RDEAD Current 3 Input Low Voltage Input High Voltage Input Hysteresis ...
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... A4935 ELECTRICAL CHARACTERISTICS (continued) valid at T unless noted otherwise Characteristics Small Signal –3 dB Frequency Bandwidth Settling Time Output Dynamic Range Output Current Sink Output Current Source VREG Supply Ripple Rejection DC Common Mode Rejection AC Common Mode Rejection Common Mode Recovery Time Output Slew Rate ...
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... A4935 xHI xLO t DEAD GHx GLx t P(off) Synchronous Rectification PWMH t P(off) GHx GLx t DEAD xHI = 1, xLO = 0, PWML = 1 COAST t P(off) GHx GLx xHI = 1, xLO = 0, PWMH = PWML = FF1 FF2 t Gate Drive RESET Fault Register Read Automotive 3-Phase MOSFET Driver ...
Page 8
... Each drive can be con- trolled with a logic level input compatible with 3 logic. The A4935 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external FETs are above supply voltages down For extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5 ...
Page 9
... A4935 In some applications a safety resistor is added between the gate and source of each FET in the bridge. When a high-side FET is held in the on-state, the current through the associated high-side gate-source resistor ( provided by the high-side drive and GSH therefore appears as a static resistive load on the top-off charge pump ...
Page 10
... Note that the A4935 can be configured to start without any exter- nal logic input so, pull up the RESET pin external resistor. The resistor value should be between 20 and 33 kΩ ...
Page 11
... For short faults, this disabled state will be latched until RESET goes low or a serial read is completed. When ESF is set to logic low, under most conditions the A4935 will not disrupt normal operation and therefore will not protect the drive circuit or motor from damage. This is the case even though the fault flags are set ...
Page 12
... Before a high-side drive can be turned on, the voltage across the associated bootstrap capacitor must be higher than the turn-on voltage limit. If this is not the case, then the A4935 will start a bootstrap charge cycle by activating the complementary low-side drive. Under normal circumstances, this will charge the bootstrap capacitor above the turn-on voltage in a few microsec- onds and the high-side drive will then be enabled ...
Page 13
... A4935 when a short fault is detected. To avoid permanent dam- age to the external FETs or to the motor under this condition, the A4935 can either be fully disabled by the RESET input or all FETs can be switched off by pulling low the COAST input or all the phase control inputs. ...
Page 14
... After the final bit, VC, is output, the external controller cycles FF2 high then low. 7. The A4935 resets the fault register and pulls FF1 and FF2 low to indicate no fault present. 8. The external controller releases FF2. The basic sequence for the three possible states of FF1 and FF2 are shown in figure 1 ...
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... FF2 (C) Undervoltage Fault Register Read A4935 pulls FF1 and FF2 low and resets fault register A4935 pulls FF1 and FF2 low and resets fault register Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 ...
Page 16
... A4935 Power Bridge Management Using PWM Control The A4935 provides individual high-side and low-side controls for each phase, plus two PWM control signals and a coast con- trol. This allows a wide variety of 3-phase bridge control schemes to be implemented. For advanced schemes using sinusoidal current control, each FET in the 3-phase bridge can be controlled individually without using the PWM and COAST inputs ...
Page 17
... FETs are switched at the same time; for example, when using synchronous rectification or after a bootstrap capacitor charging cycle. In the A4935, the dead time for all three phases is set by a single dead- time resistor (R ) between the RDEAD and AGND pins. ...
Page 18
... The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap × GATE under-voltage threshold, V age drops below this threshold, the A4935 will turn on the neces- sary low-side FET, and continue charging until the bootstrap , capacitor exceeds the undervoltage threshold plus the hysteresis, (3) ...
Page 19
... N is the number of FETs switching during a PWM cycle, and Ratio = Braking The A4935 can be used to perform dynamic braking by either , so the capacitor can be forcing all low-side FETs on and all high-side FETs off or, con- versely, by forcing all low-side FETs off and all high-side FETs on ...
Page 20
... R F erations: A4935 • The A4935 analog ground, AGND, and power ground, PGND, should be connected together at the package pins. This common point, and the high-current return of the external FETs, should CSOUT return separately to the negative side of the motor supply filtering capacitor ...
Page 21
... FETs to clamp the reverse voltage to approximately this case, the additional diode in the VBB connection will prevent damage to the A4935 and the VDRAIN input will survive the reverse voltage. Note that the above are only recommendations. Each application is different and may encounter different sensitivities ...
Page 22
... A4935 Input and Output Structures (A) Gate drive outputs ESD COAST 3 kΩ ESF PWMx xHI xLO 8.5 V (E) Logic inputs, no pulldown VREG ESD kΩ CSN 4 kΩ CSP (H) Current sense amplifier Automotive 3-Phase MOSFET Driver ...
Page 23
... A4935 Terminal List Pin Pin Name 1, 24, 25, 35 internal connection; connect to AGND 36, 37 RESET Standby mode control 3 ESF Enable Stop on Fault input 4 FF2 Fault Flag 2 and serial clock input 5 FF1 Fault Flag 1 and serial data output 6 ALO Control input phase A low-side ...
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... A4935 Package JP 48-Pin LQFP with Exposed Thermal Pad 9.00 ±0.20 7.00 ±0.20 B 9.00 ±0.20 7.00 ±0. 5.00 48X 0.08 C 0.22 ±0.05 0.50 Copyright ©2007-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...