a4988 Allegro MicroSystems, Inc., a4988 Datasheet
a4988
Available stocks
Related parts for a4988
a4988 Summary of contents
Page 1
... It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth-, and sixteenth-step modes, with an output drive capacity and ±2 A. The A4988 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. ...
Page 2
... Storage Temperature 4988-DS DMOS Microstepping Driver with Translator The A4988 is supplied in a surface mount QFN package (ES × 5 mm, with a nominal overall package height of 0.90 mm and an exposed pad for enhanced thermal dissipation lead (Pb) free (suffix –T), with 100% matte tin plated leadframes. ...
Page 3
... A4988 VREG VDD Current Regulator REF DAC PWM Latch Blanking Mixed Decay STEP DIR RESET Control Translator MS1 Logic MS2 MS3 PWM Latch ENABLE Blanking Mixed Decay SLEEP DAC V REF 4988-DS DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F CP1 ROSC ...
Page 4
... A4988 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time ...
Page 5
... A4988 THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance *Additional thermal information available on Allegro Web site. 4988-DS DMOS Microstepping Driver with Translator Symbol Test Conditions* R Four-layer PCB, based on JEDEC standard θJA Power Dissipation versus Ambient Temperature 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0. 100 Temperature and Overcurrent Protection ...
Page 6
... A4988 STEP MS1, MS2, MS3, RESET, or DIR STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Table 1. Microstepping Resolution Truth Table MS1 4988-DS ...
Page 7
... ROSC configuration and the step sequence, as shown in figures 8 through 12. During Mixed decay, when the trip point is reached, the A4988 initially goes into a fast decay mode for 31.25% of the off-time, t decay mode for the remainder of t feature appears on the next page ...
Page 8
... A4988 Slow Mixed Decay Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. Figure 2. Missed steps in low-speed microstepping I 500 mA/div. LOAD Step input 10 V/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) 4988-DS DMOS Microstepping Driver with Translator ...
Page 9
... A4988 tion of current flow in each winding. The size of the increment is determined by the combined state of the MSx inputs. (DIR). This determines the direction of rota- Direction Input tion of the motor. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. ...
Page 10
... FETs, current regulator, and charge pump. A logic low on the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ pin puts the A4988 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4988 drives the motor to the Home microstep position) ...
Page 11
... A4988 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 7. Current Decay Modes Timing Chart 4988-DS DMOS Microstepping Driver with Translator See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time off Maximum output current PEAK t Slow decay interval SD t Fast decay interval ...
Page 12
... Layout. The printed circuit board should use a heavy ground- plane. For optimum electrical and thermal performance, the A4988 must be soldered directly onto the board. Pins 6, 7, 18, and 19 are internally fused, which provides a path for enhanced thermal dissipation. Theses pins should be soldered directly to an exposed surface on the PCB that connects to thermal vias are used to transfer heat to other layers of the PCB ...
Page 13
... A4988 VDD VBB 8 V GND GND V BB VREG SENSE 10 V GND 4988-DS DMOS Microstepping Driver with Translator Pin Circuit Diagrams GND PGND GND MS1 MS2 MS3 V REG DIR VREF ROSC DMOS SLEEP Parasitic GND and Overcurrent Protection VCP CP1 CP2 ...
Page 14
... A4988 STEP 100.00 70.71 Phase 1 I OUT1A 0.00 Direction = H (%) –70.71 –100.00 100.00 70.71 Phase 2 I OUT2A 0.00 Direction = H (%) –70.71 –100.00 Figure 8. Decay Mode for Full-Step Increments STEP Phase 1 I OUT1A Direction = H (%) Phase 2 I OUT2B Direction = H (%) Figure 10. Decay Modes for Quarter-Step Increments 4988-DS DMOS Microstepping Driver with Translator ...
Page 15
... A4988 STEP 100.00 92.39 83.15 70.71 55.56 38.27 Phase 1 19.51 I OUT1A 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 38.27 Phase 2 19.51 I OUT2B 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 Figure 11. Decay Modes for Eighth-Step Increments 4988-DS DMOS Microstepping Driver with Translator Mixed* Slow Mixed ...
Page 16
... A4988 STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Phase 1 9.8 I OUT1A 0.00 Direction = H –9.8 (%) –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Slow Phase 2 9.8 I OUT2B 0.00 Direction = H –9.8 (%) –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 Figure 12. Decay Modes for Sixteenth-Step Increments ...
Page 17
... A4988 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Phase 1 Full Half 1/4 1/8 1/16 Current Step Step Step Step Step [% I tripMax ] # # # # # ...
Page 18
... A4988 Terminal List Table Name CP1 CP2 VCP VREG MS1 MS2 MS3 ¯ R ¯ ¯ E ¯ ¯ S ¯ ¯ E ¯ ¯ T ¯ ROSC ¯ S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ VDD STEP REF GND DIR OUT1B VBB1 SENSE1 ...
Page 19
... A4988 ET Package, 28-Pin QFN with Exposed Thermal Pad 29X 0.08 C +0.05 0.25 –0.07 0.73 MAX Copyright ©2009-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...