AD1849K Analog Devices, AD1849K Datasheet

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AD1849K

Manufacturer Part Number
AD1849K
Description
Serial-Port 16-Bit SoundPort Stereo Codec
Manufacturer
Analog Devices
Datasheet

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a
PRODUCT OVERVIEW
The Serial-Port AD1849K SoundPort® Stereo Codec integrates
the key audio data conversion and control functions into a single
integrated circuit. The AD1849K is intended to provide a com-
plete, single-chip audio solution for multimedia applications
requiring operation from a single +5 V supply. External signal
path circuit requirements are limited to three low tolerance
capacitors for line level applications; anti-imaging filters are
incorporated on-chip. The AD1849K includes on-chip monaural
SoundPort is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Single-Chip Integrated
Multiple Channels of Stereo Input and Output
Digital Signal Mixing
On-Chip Speaker and Headphone Drive Capability
Programmable Gain and Attenuation
On-Chip Signal Filters
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V and Mixed +5 V/+3.3 V Supplies
Serial Interface Compatible with ADSP-21xx Fixed-
Compatible with CS4215 (See Text)
ANALOG
ANALOG
HEADPHONE RETURN
Digital Interpolation and Decimation
Analog Output Low-Pass
Point DS Ps
OUT
IN
LINE 0 R
LINE 1 L
LINE 1 R
LINE 0 L
LINE R
LINE L
MIC R
MIC L
ANALOG
SUPPLY
LOOPBACK
MUTE
MUTE
dB
20
Digital Audio Stereo Codec
R
R
L
L
DIGITAL
SUPPLY
ANALOG
ANALOG
FILTER
FILTER
MUX
MONO SPEAKER
OUT
MUTE
R
L
ATTENUATE
ATTENUATE
FUNCTIONAL BLOCK DIAGRAM
GAIN
GAIN
RETURN
CONVERTER
CONVERTER
CONVERTER
CONVERTER
REFERENCE
A/D
D/A
D/A
A/D
2.25V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
speaker and stereo headphone drive circuits that require no
additional external components. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals, from an external
clock, or from the serial interface bit clock.
The Codec includes a stereo pair of
converters and a stereo pair of
Analog signals can be input at line levels or microphone levels.
A software controlled programmable gain stage allows
independent gain for each channel going into the ADC. The
ADCs’ output can be digitally mixed with the DACs’ input.
The left and right channel 16-bit outputs from the ADCs are
available over a single bidirectional serial interface that also sup-
ports 16-bit digital input to the DACs and control information.
The AD1849K can accept and generate 8-bit -law or A-law
companded digital data.
The
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two independent
stereo pairs of line-level (or one line-level and one headphone)
outputs are generated, as well as drive for a monaural (mono)
speaker.
INTERPOL
INTERPOL
DACs are preceded by a digital interpolation filter. An
ATTENUATE
ATTENUATE
SoundPort Stereo Codec
OSCILLATORS
AD1849K
CRYSTALS
2
MONITOR MIX
2
POWER DOWN
Serial-Port 16-Bit
LAW
LAW
LAW
LAW
CHAINING
OUTPUT
/A
/A
/A
/A
digital-to-analog converters.
S
E
R
A
P
O
R
L
T
I
CHAINING
analog-to-digital
INPUT
AD1849K
L
O
O
P
B
A
C
K
2
(Continued on page 8)
Fax: 617/326-8703
DATA/CONTROL
MODE
DATA/CONTROL
TRANSMIT
DATA/CONTROL
RECEIVE
PARALLEL I/O
BIT CLOCK
FRAME SYNC
RESET
DIGITAL
I/O

Related parts for AD1849K

AD1849K Summary of contents

Page 1

... PRODUCT OVERVIEW The Serial-Port AD1849K SoundPort® Stereo Codec integrates the key audio data conversion and control functions into a single integrated circuit. The AD1849K is intended to provide a com- plete, single-chip audio solution for multimedia applications requiring operation from a single +5 V supply. External signal path circuit requirements are limited to three low tolerance capacitors for line level applications ...

Page 2

... AD1849K–SPECIFICATIONS ELECTRICAL SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Clock (SCLK) 256 Master Mode 256 Bits per Frame Word Rate ( Input Signal 1 Analog Output Passband kHz V 2 0.8 IL External Load Impedance ...

Page 3

... All Selectable Sampling Frequencies) *Guaranteed, not tested. REV. 0 Min Typ 0.013 –78 0.032 –70 Min Typ 0.010 –80 0.022 –73 0.045 –67 –3– AD1849K Max Units Bits dB dB 0.020 % –74 dB 0.056 % –65 dB –80 dB –60 dB 0.75 dB 0.3 dB Max Units Bits dB ...

Page 4

... AD1849K MONITOR MIX ATTENUATOR Step Size (0 –60 dB)* Step Size (–61 –94.5 dB)* Output Attenuation* DAC ATTENUATOR Step Size (0 –60 dB) (Tested at Steps –1.5 dB, –19.5 dB, –39 dB and –60 dB) Step Size (–61 –94.5 dB)* Output Attenuation* SYSTEM SPECIFICATIONS System Frequency Response* (Line In to Line Out ...

Page 5

... Specifications subject to change without notice. REV. 0 Min Typ 80 1/(F Bits per Frame 100 Min Typ 4.75 100 20 40 Min 5.5125 –5– AD1849K Max Units 13.5 MHz Max Units 5.25 V 130 mA ...

Page 6

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1849K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 7

... TQFP I –7– AD1849K Description Receive Serial Data Pin Transmit Serial Data Pin Bidirectional Serial Bit Clock Frame Sync Output Signal Chaining Word Output Chaining Word Input Data/Control Select Input Crystal 1 Input Crystal 1 Output ...

Page 8

... AD1849K (Continued from page 1) FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1849K and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. The user is not expected to refer repeatedly to this section. ...

Page 9

... LSB autocalibration sequence is also performed when the AD1849K leaves the reset state (i.e., RESET goes HI). The RESET pin should be held LO for 50 ms after power up or after leaving power-down mode to delay the onset of the autocalibration sequence until after the voltage reference has settled. ...

Page 10

... Two crystal inputs are provided to generate a wide range of sample rates. The oscillators for these crystals are on the AD1849K multiplexer for selecting µ/A-LAW SDRX between them. They can be overdriven with external clocks by DECODE the user desired ...

Page 11

... Data Mode. (See Figure 8.) Control bits can also be read back for system verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states after RESET or Power Down ...

Page 12

... Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin (COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal frequencies, and it will be divided down by the selected Divide Factor ...

Page 13

... Reserved bits should be written as 0. Control Byte 7, Revision Register Data 7 Data REVID3:0 Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K. Control Byte 8, Reserved Register Data 7 Data Reserved bits should be written as 0. ...

Page 14

... AD1849K Data Mode Data and Control Registers Data Byte 1, Left Audio Data—Most Significant 8 Bits Data 7 Data 6 L15 L14 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte contains the left audio data sample ...

Page 15

... Data 5 Data 4 Data 3 OVR IS LG3 Data 5 Data 4 Data 3 MA1 MA0 RG3 MA, except for MA = “15,” which disables monitor mix entirely. –15– AD1849K Data 2 Data 1 Data 0 RO2 RO1 RO0 Data 2 Data 1 Data 0 LG2 LG1 LG0 Data 2 ...

Page 16

... A Control-to-Data Mode transition is no exception. An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word input signal (TSIN) initially. (See “ ...

Page 17

... SERIAL INTERFACE A single serial interface on the AD1849K provides for the trans- fer of both data and control information. This interface is simi- lar to AT&T’s Concentrated Highway Interface (CHI), allowing simple connection with ISDN and other telecommunication devices. The AD1849K’s implementation also allows a no-glue direct connection to members of Analog Devices’ ...

Page 18

... OF WORD INPUTS PIO OUTPUTS The AD1849K comes out of reset with the default conditions specified in “Control Register Defaults.” It will be in the mode specified by the D/C pin Control Mode, the SoundPort Codec can be configured by the host for operation. Subsequent transitions to Control Mode after initialization are expected to be relatively infrequent ...

Page 19

... CLKIN CODEC STARTUP, MODES, AND TRANSITIONS Reset and Power Down The AD1849K Stereo Codec can be reset by either of two closely related digital input signals, RESET and Power Down (PDN). RESET is active LO and PDN is active HI. Asserting PDN is equivalent to asserting RESET with two exceptions. ...

Page 20

... In general, in Control Mode, the location of the echo Control Word within a frame will be at the same word location as the input Control Word. In the first frame of Control Mode, the AD1849K will output a Control Word that reflects the control register values operative during the most recent Data Mode operation. If Control Mode was entered prior to any Data Mode operation, this first output word will simply reflect the standard default settings ...

Page 21

... The AD1849K SoundPort only powered device. Line level voltage swings for the AD1849K are defined rms for ADC input and 0.707 V rms for DAC output. Thus rms input analog signals must be attenuated and either centered around the reference voltage intermediate between 0 V and + ac-coupled ...

Page 22

... NPO Figure 11. AD1849K 2 V rms Line-Level Input Circuit An external passive antialias filter is required. If line-level inputs are already at the 1 V rms levels expected by the AD1849K, the resistors in parallel with the 560 pF capacitors should be omitted and the series 5.1 k resistor should be decreased to 2 ...

Page 23

... Note that this output is differential. Analog Devices guarantees specified distortion performance for speaker impedances greater. Lower impedance speakers can be used, but at the cost of some distortion. When driving speakers much less than power amp should be used. The AD1849K can drive speakers greater. MOUT MOUTR Figure 16 ...

Page 24

... The digital ground and analog grounds should be tied together in the vicinity of the AD1849K. Other schemes may also yield satisfactory results. Figure 23 illustrates the “zero-chip” interfaces of the AD1849K SoundPort Codec to four of Analog Devices’ ...

Page 25

... We strongly recommend connecting this pin to the digital supply. Both chips should operate in this configura- tion. Pin 39 (PLCC) and Pin 33 (TQFP) on the AD1849K is used as a digital ground. On the CS4215, this pin is a “no connect.” We strongly recommend connecting this pin to the digital ground plane ...

Page 26

... Figure 26. AD1849K Digital-to-Analog Frequency Response (Full-Scale Inputs Attenuation –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.54 0.56 0.58 0.60 0. Figure 27. AD1849K Digital-to-Analog Frequency Response – Transition Band (Full-Scale Inputs Attenuation) –26– 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 SAMPLE FREQUENCY ( 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 SAMPLE FREQUENCY (F ...

Page 27

... INDEX PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . 2 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AD1849K PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 8 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . 8 Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . 8 Monitor Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supplies and Voltage Reference . . . . . . . . . . . . . . . 9 Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . 10 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Mode Control Registers ...

Page 28

... AD1849K 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 6 0.042 (1.07) 7 IDENTIFIER TOP VIEW 17 18 0.656 (16.66) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (PLCC) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.025 (0.63) 0.042 (1.07) 0.015 (0.38) 40 PIN 1 39 0.021 (0.53) 0.013 (0.33) 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) 0.050 (1.27) BSC 29 28 0.040 (1.01) ...

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