AD1890 Analog Devices, AD1890 Datasheet
AD1890
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AD1890 Summary of contents
Page 1
... The input word width bits for the AD1890 bits for the AD1891. Shorter input words are automatically zero-filled in the LSBs. The output word width for both devices is 24 bits. The user can receive as many of the output bits as desired ...
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... All minimums and maximums tested except as noted. PERFORMANCE (Guaranteed over 0 C AD1890 Dynamic Range ( kHz, –60 dB Input)† AD1891 Dynamic Range ( kHz, –60 dB Input)† Total Harmonic Distortion + Noise† AD1890 and AD1891 ( kHz, Full-Scale Input, ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1890/AD1891 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... The AD1890 also has a pin selectable, short or long group delay mode. This pin determines the depth of the First-In, First-Out (FIFO) memory which buffers the input data samples before they are processed by the FIR convolver ...
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... It is usually expressed in percent (%) or decibels. Interchannel Phase Deviation Difference in input sampling times between stereo channels, ex- pressed as a phase difference in degrees between 1 kHz inputs. AD1890/AD1891 PIN LIST Serial Input Interface Pin Name Number I/O Description ...
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... GPDLYS 1 I AD1890 ONLY: Group delay—short. HI: Short group delay mode ( 700 s). More sensitive to changes in sample rates (LR clocks). LO: Long group delay mode ( 3 ms). More tolerant of sample rate changes. This signal may be asynchronous with respect to MCLK, and dynamically changed, but is normally pulled up or pulled down on a static basis. AD1891: Short group delay mode only ...
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... There are at least two logically equivalent methods of explaining the concept of asynchronous sample rate conversion: the high speed interpolation/decimation model and the polyphase filter bank model. Using the AD1890 and AD1891 SamplePorts does not require understanding either model. This section is included for those who wish a deeper understanding of their operation. ...
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... AD1890/AD1891 SamplePort hardware. In the polyphase filter bank model, the stored FIR filter coefficients are thought of as the impulse response of a highly oversampled kHz low-pass prototype filter, as shown in Figure 2 ...
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... Figure 4, at the input sample rate OUTPUT MUX SIGNAL SELECT SAMPLE CLOCK TRACKING CIRCUIT –9– AD1890/AD1891 F sin /2 FREQ DELAY = NOMINAL F sin /2 DELAY = NOMINAL F sin /2 DELAY = NOMINAL – .25/F sin F sin /2 DELAY = NOMINAL – .5/F sin F sin /2 DELAY = NOMINAL – .75/F sin ...
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... A fast set- tling loop will act to keep the FIFO read and write addresses separated better than a slow settling loop. The AD1890/ AD1891 include a user selectable pin (SETLSLW) to set the loop settling time that essentially changes the coefficients of the digital servo control loop filter ...
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... AD1890/AD1891 ASRCs possess a linear phase response. The AD1890 has been designed so that when long group delay mode and fast settling mode, a full 2:1 step change (i.e., occurring between two samples) in sample frequency ratio can be tolerated without output mute. – ...
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... The cutoff frequency of the FIR filter during ), i.e., SIN upsampling is given by the following relation: Upsampling Cutoff Frequency = (F Noise and Distortion Phenomena There are three noise/distortion phenomena that limit the per- formance of the AD1890/AD1891 ASRCs. First, there is whenever F is less SOUT Figure 8. Number of Filter Taps as a Function of /44.1 kHz) 20 kHz ...
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... LR_O). A left channel field, right channel field pair is called a frame. The input data field consists bits for the AD1890, and bits for the AD1891. The output data field consists bits for both devices. The input signals are specified to TTL logic levels, and the outputs swing to full CMOS logic levels ...
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... Master Clock Using a 16 MHz MCLK, the nominal range of sample frequen- cies that the AD1890/AD1891 accept is from 8 kHz to 56 kHz. Other sample frequency ranges are possible by linearly scaling the MCLK frequency. For example MHz MCLK would yield a sample frequency range of 6 kHz to 42 kHz, and a 20 MHz MCLK would yield a sample frequency range of 10 kHz to 70 kHz ...
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... It is also likely that several AD1890/AD1891s could end serial cascade arrangement, either in a single systems design or as the result of two or more systems, each using a single AD1890/ AD1891 in the signal path. The audio signal quality will be degraded with each pass through an ASRC, though to a very minor degree ...
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... FREQUENCY – Hz FREQUENCY – Hz Figure 16a. AD1890—15 kHz Tone at 0 dBFS, 48 kHz Input Sample Frequency, 44.1 kHz Output Sample Frequency, 16k-Point FFT, BH4 Window –60.00 –70.00 –80.00 –90.00 –100.0 –110.0 –120.0 –130.0 –140.0 – ...
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... AMPLITUDE – dBFS Figure 18a. AD1890—THD+N vs. Input Amplitude, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 1 kHz and 20 kHz Tones Figure 19. AD1890/AD1891 Digital Filter Signal Transfer Function, 10 kHz to 20 kHz, 44.1 kHz Input Sample Frequency, 44.1, 40, 35, 30 and 25 kHz Output Sample Frequencies REV. 0 – ...
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... Figure 20a. AD1890—Twintone, 10 kHz and 11 kHz, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 16k-Point FFT, BH4 Window Figure 21. AD1890/AD1891—5 kHz Tone at 0 dBFS with 100 ns p-p Binomial Jitter Clocks, Fast Settling Mode, 48 kHz Input Sample Frequency, 44.1 kHz Output Sample Frequency, 16k-Point FFT, BH4 Window ...
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... DATA IN/OUT MSB MSB-1 NO MSB DELAY MODE DATA IN/OUT MSB MSB–1 MSB–2 MSB DELAY MODE Figure 23. AD1890/AD1891 Serial Data Input and Output Timing, Left/ Right Clock Triggered Mode MCLK t MCLK Figure 24. AD1890/AD1891 MCLK Timing BCLK_I, BCLK_O NORMAL MODE BCLK_I, BCLK_O ...
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... AD1890/AD1891 28 PIN 1 1 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.048 (1.21) 0.042 (1.07) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-28 28-Lead Plastic DIP 15 0.580 (14.73) 0.485 (12.32) 14 1.565 (39.70) 1.380 (35.10) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 SEATING 0.070 (1.77) (2.54) MAX PLANE BSC P-28A 28-Lead PLCC 0.180 (4.57) 0.165 (4.19) ...