AD1986A Analog Devices, AD1986A Datasheet
AD1986A
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AD1986A Summary of contents
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... Center/LFE swapping supporting all vendor speakers Microphone left/right swapping Reduced support component count General-purpose digital output pin (GPO) LINE_OUT and HP_OUT, headphone drive on both One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD1986A www.analog.com ...
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... AD1986A TABLE OF CONTENTS Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 9 Environmental Conditions.......................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration And Function Description ........................... 10 AC’97 Registers............................................................................... 12 HD Audio Widgets ......................................................................... 14 AC ’97 Register Details .................................................................. 21 Reset (Register 0x00).................................................................. 21 Master Volume (Register 0x02) ................................................ 21 Headphone Volume (Register 0x04) ........................................ 22 Mono Volume (Register 0x06) ...
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... DataSheet U .com • Advanced Jack Presence Detection: Using two codec pins, eight resistors and isolated switch jacks, the AD1986A can detect jack insertion on eight separate jacks. • Internal Microphone/Line In/C/LFE Sharing: On systems that share the microphone with the C/LFE jack no external components are required ...
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... LFE_OUT MZ A CENTER_OUT MZ A MONO_OUT M A SURR_OUT_L SURR_OUT_R A A LINE_OUT_L LINE_OUT_R HP HP_OUT_L HP_OUT_R DataSheet U .com AD1986A Σ Σ Σ GAIN A = ATTENUATION M = MUTE HI-Z Figure 1 ...
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... Table 4. Programmable Gain Amplifier—ADC Parameter Step Size PGA Gain Range Span ( 22.5 dB) 4 DataSheet U .com ADC Test Conditions Calibrated 0 dB PGA Gain Input −3.0 dB Relative to Full Scale 2 Rev Page AD1986A Typ Unit 25 °C 3.3 ± 10% V 5.0 ± 10 kHz 1.0 kHz 20 Hz– ...
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... AD1986A Table 5. Analog Mixer—Input Gain/Amplifiers/Attenuators Parameter Signal-to-Noise Ratio (SNR LINE_OUT 1 LINE, AUX, PHONE to LINE_OUT 1 MIC_1 or MIC_2 to LINE_OUT Step Size: All Mixer Inputs (Except PC Beep) Step Size: PC Beep Input Gain/Attenuation Range: All Mixer Inputs (+ −34.5 dB) 1 Guaranteed by design, not production tested. ...
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... Min Typ 1 2.83 300 2. 2.050 2.250 2.250 3.700 0.0 ±5 Min Typ Max 0.65 × 0.35 × DV 0.90 × 0.10 × DV −10 10 −10 10 7.5 AD1986A Max Unit Bits ±0.7 dB −80 dB Max Unit VRMS V p-p Ω kΩ pF 1,000 pF VRMS V p-p 1 Ω Ω pF 1,000 pF 2.450 V V ...
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... AD1986A Table 11. Power Supply (Quiescent State) Parameter Power Supply Range—Analog (AV Power Supply Range—Digital (DV DD Power Dissipation—Analog (AV )/Digital (DV DD Analog Supply Current—Analog (AV Digital Supply Current—Digital (DV Power Supply Rejection (100 mV p–p Signal @ 1 kHz) Table 12. Power-Down States—AC ’97 (Quiescent State) ...
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... DD JA °C θ = thermal resistance (junction-to-case +70 –40 +85 Table 15. Thermal Resistance −65 +150 °C Package LQFP LFCSP Rev Page AD1986A − (PD × θ ) CASE CA θ θ θ 48°C/W 17°C/W 31°C/W 47°C/W 15°C/W 32°C/W ...
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... JACK_SENSE_A JACK_SENSE_B 4 DataSheet U .com PIN 1 AC97CK 2 IDENTIFIER GPO SDATA_OUT 5 AD1986A BIT_CLK 6 TOP VIEW (Not to Scale) SDATA_IN SYNC 10 RESET 11 PCBEEP Figure 2. Pin Configuration Input/Ouput ...
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... Programmable Voltage Reference Output (Intended for MIC Bias on the C/LFE Channels). Input/ Ouput Description N/A Digital Supply Voltage (3.3 V). N/A Digital Supply Return (Ground). N/A Analog Supply Voltage (5.0 V). AV degrade performance. N/A Analog Supply Return (Ground). Rev Page supplies should be well filtered because supply noise will DD AD1986A ...
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... AD1986A AC’97 REGISTERS Table 22. Register Map Reg Name D15 D14 0x00 Reset x SE4 0x02 Master Volume LM x 0x04 Headphones Volume LM x 0x06 Mono Volume M x 0x0A PC Beep M A/DS 0x0C Phone Volume M x 0x0E Microphone Volume LM x 0x10 Line In Volume LM x 0x12 CD Volume ...
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... INV DL4 DL3 ST1 ST0 Rev Page FC3 FC2 FC1 FC0 DL2 DL1 DL0 OR1 OR0 SR5 SR4 SR3 SR2 SR1 AD1986A D0 Default T/R 0x0000 FIP 0xXxxx SR0 0xXxxx ...
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... Rev Page Description Device identification. Description The AD1986A has only a single SDI line, thus set SDI verbs are ignored and get SDI verbs always return a 0. Get/set the vendor specific function at the below coefficient index address. Address is an 8-bit value and does not auto-increment ...
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... Payload Response Description BIt (32 Bits) Description N/A (0) N/A (0) The AD1986A has only a single SDI line, thus set SDI verbs are ignored and get SDI verbs always return a 0. N/A (0) 8 N/A (0) N/A (0) Coefficient Get/set the processing coefficient at the current coefficient index. Index can be set by the “set coefficient index” verb. ...
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... AD1986A Table 32. Center/LFE DAC Audio Output NID Name 0x05 Center/LFE DAC Audio Output Table 33. Record ADC Audio Input NID Name 0x06 Record ADC Audio Input Table 34. Analog Mixer NID Name 0x07 Analog Mixer Table 35. Mono Mixer NID Name 0x08 Mono Mixer Table 36 ...
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... Processing State Up-Mix Spreading Off Off Benign On Benign On Description Chooses the analog source to the record ADCs. Description The microphone amplifier input to the analog mixer. Description The phone amplifier input to the analog mixer. Description The CD amplifier input to the analog mixer. AD1986A ...
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... AD1986A Table 51. Aux MixAmp NID Name 0x16h Aux MixAmp Table 52. Line In MixAmp NID Name 0x17 Line In MixAmp Table 53. PC Beep Selector NID Name 0x18 PC Beep Selector Table 54. Digital PC Beep NID Name 0x19 Digital PC Beep Table 55. HP Out NID Name 0x1A HP Out Table 56 ...
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... PHONE_IN pin driver. Mono line level input. TID Type Description 0x4 Pin Complex PCBEEP_IN pin driver. Mono line level input. When the AD1986A is in reset, the signal on this pin is routed to all output capable pins. Used for BIOS POST beeps or messages. TID Type Description 0x4 Pin Complex Digital S/PDIF output drivers ...
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... AD1986A Table 70. C/LFE/Line In Mixer NID Name 0x29 C/LFE / Line In Mixer Table 71. MIC/Line In/C/LFE Mixer NID Name 0x2A MIC/Line In/C/LFE Mixer Table 72. MIC_1/2 Mixer NID Name 0x2B MIC_1/2 Mixer 4 DataSheet U .com TID Type Description 0x2 Audio Mixer Mixes the C/LFE and LINE_IN input signals together to support simultaneous microphones on front and rear panels ...
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... Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement. Reg Name D15 D14 0x00 Reset x SE4 Table 73. Register Function ID [9:0] (RO) The ID decodes the capabilities of the AD1986A based on the functions. (Identify Bit Capability) ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ...
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... AD1986A Table 74. Register Function L/RV [4:0] Left/right volume controls the left/right channel output gains from –46.5 dB. (Left/Right The least significant bit represents –1.5 dB. Volume) L/ L/RM Mutes the left/right channels independently. (Left/right mute) x Reserved. HEADPHONE VOLUME (REGISTER 0x04) This register controls the HP_OUT mute and volume controls. Each volume subregister contains five bits, generating 32 volume steps of − ...
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... PC beep register and the path to each output, and set the volume levels for playback. When the AD1986A is in reset (the external RESET pin is low), the PCBEEP_IN pin is connected internally to all of the device output pins (HEADPHONE L/R, LINE_OUT L/R, MONO_OUT, SURROUND L/R, and CENTER/LFE). There are no amplifiers or attenuators on this path and the external circuitry connected to this pin should anticipate the drive requirements for the multiple output sources ...
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... AD1986A Table 78. Register Function V [4:0] Controls the gain of this input to the analog mixer from +12 −34.5 dB. The least significant bit represents −1.5 (Volume) dB (Mute) Mutes the input to the analog mixer. x Reserved. MICROPHONE VOLUME (REGISTER 0x0E) This register controls the MIC_1 (left) and MIC_2 (right) channels’ gain, boost, and mute to the analog mixer section. The volume register contains five bits, generating 32 volume steps of − ...
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... Muted Rev Page RV4 RV3 RV2 RV1 Default Default Default: muted (0x1) Default RV4 RV3 RV2 RV1 Default Default Default: muted (0x1) Default: 0 AD1986A D0 Default RV0 0x8888 D0 Default RV0 0x8888 ...
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... AD1986A AUX VOLUME (REGISTER 0x16) This register controls the AUX_IN gain and mute to the analog mixer section. The volume register contains five bits, generating 32 volume steps of −1.5 dB each for a range of +12 −34.5 dB. This does not control the record ADC gain (see Register 0x1C). ...
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... MIC_2 MIC_2 MIC_1 MIC_1 + MIC_2 (mixed) LINE_IN left LINE_IN right LINE_IN right LINE_IN left Line in—left + right (mixed) CENTER LFE LFE CENTER CENTER + LFE (mixed) MIC_1 + CENTER (mixed) MIC_2 + LFE (mixed) MIC_2 + LFE (mixed) MIC_1 + CENTER (mixed) AD1986A D0 Default RS0 0x0000 ...
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... AD1986A OMS [2:0] MMIX 2CMIC 101 0 0 101 0 0 101 0 1 101 0 1 101 1 x 110 0 0 110 0 0 110 0 1 110 0 1 110 1 x 111 0 0 111 0 0 111 0 1 111 0 1 111 select the alternate pins as a microphone source, see the OMS [2:0] bit (Register 0x74). ...
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... Interrupt generation is masked Interrupt generation is unmasked Rev Page LPBK Default PG3 PG2 PG1 AD1986A D1 D0 Default x x 0x0000 Default Default: disabled (0x0) Default Default Default PG0 0xxx00 Default Default Default ...
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... POWER-DOWN CTRL/STAT (REGISTER 0x26) The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986A subsections. If the bit is 1 then that subsection is ready. ‘Ready’ is defined as the subsection able to perform in its nominal state. ...
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... Default CDAC DSA1 DSA0 x SPDF DRA Function Variable rate PCM audio supported SPDIF transmitter supported (IEC958) Double rate audio supported for DAC0 L/R C/LFE DAC Default Right Left Right Default AD1986A D0 Default VRA 0x0BC7 ...
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... AD1986A Register Description CDAC (RO) PCM CENTER DAC: read only SDAC (RO) PCM Surround DAC: read only LDAC (RO) PCM LFE DAC: read only AMAP (RO) Slot DAC mappings: read only REV [1:0] (RO) AC97 version: read only ID [1:0] (RO) Codec configuration: read only x Reserved EXT’D AUDIO STAT/CTRL (REGISTER 0x2A) The extended audio status and control register is a read/write register that provides status and control of the extended audio features ...
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... Power down surround DACs LFE DACs Power Control Power on LFE DAC Power down LFE DAC D14 D13 D12 D11 D10 D9 D8 R14 R13 R12 R11 R10 R9 R8 Rev Page AD1986A Default Default Default Default ...
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... AD1986A SURROUND DAC PCM RATE (REGISTER 0x2E) This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit (0x2A D00 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate. ...
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... CNTM x x CNT4 CNT3 CNT2 CNT1 Default Default Default: muted (0x1) Default Default: muted (0x1) Default RV4 RV3 RV2 Default Default Default: muted (0x1) Default: 0 AD1986A D0 Default CNT0 0x8888 D1 D0 Default RV1 RV0 0x8888 ...
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... AD1986A SPDIF CONTROL (REGISTER 0x3A) Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0) ...
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... Biquad 5 Coef a2 BCA [5,0] = 110010 Biquad 5 Coef b1 BCA [5,0] = 110110 Biquad 5 Coef b2 BCA [5,0] = 110101 Biquad 6 Coef a0 BCA [5,0] = 111001 Biquad 6 Coef a1 BCA [5,0] = 111000 Biquad 6 Coef a2 BCA [5,0] = 110111 Biquad 6 Coef b1 BCA [5,0] = 111011 Biquad 6 Coef b2 BCA [5,0] = 111010 Default Default Default Default Default: 0 AD1986A D0 Default BCA0 0x8080 ...
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... CVREF [2:0] 000 001 010 100 JSMAP The AD1986A supports two different methods of mapping the JACK_SENSE_A/B resistor tree to bits JS [7:0]. Use (Jack Sense Mapping) these bits to change from the default mapping to the alternate method. JSMAP 0 1 MMDIS Disables the automatic muting of the MONO_OUT pin by jack sense events (see advanced jack sense bits JS [3:0] (Mono Mute Disable) (0x76 D [05:04], 0x72 D [05:04]) ...
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... JS1 = 1 will cause the bypassed Rev Page JS1 JS0 JS1 JS0 JS1 INT Write No operation Clears JS0INT bit Write No operation Clears JS1INT Default Default Default Default Default AD1986A D0 Default JS0 0x0000 INT ...
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... AD1986A Register Function JSMT [2,0] These three bits select and enable the jack sense muting action. See Table 104. (JS Mute Enable selector) JS0DMX This bit enables JS0 to control the down-mix function. This function allows a digital mix of 6-channel audio into 2-channel (JS0 Down- audio ...
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... FMUTE ACTIVE ACTIVE FMUTE Standard six channel configuration swapped HP_OUT and LINE_OUT ** ** ** **RESERVED ** ** ** ** ** ** ** ** ** ** ** ** **RESERVED ** ** ** ** ** ** ** ** ** OM0 SPOVR LBKS1 LBKS0 INTS CSWP SPAL Default Default Default Default LFE Pin LFE channel Default Center channel AD1986A D1 D0 Default SPDZ SP 0x1001 LNK ...
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... AD1986A Register Function INTS This bit selects the audio interrupt implementation path. Note that this bit does not generate an interrupt, rather it steers the (Interrupt path of the generated interrupt. Mode INTS Select LBKS [1:0] These bits select the internal digital loop-back path when LPBK bit is active (see Register 0x20). ...
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... The SPDR selector drives the center and LFE outputs from the MONO_OUT C/LFE Output State Outputs enabled Outputs tristated Rev Page SPRD 2CMIC SOSEL SRU LISEL1 LISEL0 MBG1 Default Default Default Default Default Default Default Default AD1986A D0 Default MBG0 6010 ...
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... Separates the left and right mutes on all volume registers. This bit is read-only 1 (one) on the AD1986A, (Mute Split) indicating that mute split is always enabled. AC ‘97NC (RO) Changes addressing to ADI model (vs. true AC ’97 definition). This bit is read-only 1 (one) on the AD1986A, (AC ‘97 No Compatibility indicating that ADI addressing is always enabled. Mode) DACZ Determines DAC data fill under starved condition ...
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... Rev Page JS4- x JS3 JS2 JS3 JS2 Write Clears JSx interrupt Generates a software interrupt LOHPEN GPO MMIX x AD1986A D1 D0 Default JS3 JS2 0xxxxx INT INT Default Default Default Default Default Default x 0x0000 ...
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... AD1986A Register Function LOHPEN Enables the headphone drive on the LINE_OUT pins. Disabling the headphone drive is the same as powering it down (see the PR6 bit (0x26 D14)). LOHPEN Function 0 LINE_OUT headphone drive is disabled 1 LINE_OUT headphone drive is enabled LVREF [2:0] Sets the voltage/state of the LINE_IN VREF_OUT signal. VREF_OUT is used to power microphone style devices plugged into (Line In the connected jack circuitry ...
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... ID. This number will increment with each stepping/rev. of the codec chip. CL [4:0] The AD1986A will return 0x00 from this register. This is a codec vendor specific field to define software (Codec compatibility for the codec. Software reads this field together with codec vendor ID (Register 0x7C–0x7E) Compatibility to determine vendor-specific programming interface compatibility ...
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... Table 112. Register Function PI [15:0] Optional per AC ‘97 specifications, should be implemented as read/write on the AD1986A. This field provides the PCI (PCI Vendor subsystem ID of the audio or modem subassembly (that is, CNR model, motherboard SKU). This is not the codec vendor PCI ID the AC ’97 controller PCI ID. Information in this field must be available, because the AC ’97 controller reads when the codec ready is asserted in the AC link ...
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... This register is used to select which function (analog I/O pins), information and I/O (0x6801), and sense (0x6A01) registers apply to it. The AD1986A associates FC = 0x0 with surround functions and FC = 0x01 with front functions. These are changed in the AD1986A to align with the device pinout and to separate LINE_OUT functions. ...
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... AD1986A INFORMATION AND I/O REGISTER (REGISTER 0x68, PAGE 01) This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). These values are only reset by power-on used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must not be reset by soft or hardware resets ...
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... Stereo headphone SPDIF out (electrical) SPDIF out (TOS) Rev Page Gain/Attenuation (dB Relative to Level-Out +1.5 dB +1.5 dB × G [3:0] +24.0 dB −1.5 dB −1.5 dB × G [3:0] −24.0 dB Default OR1 OR0 SR5 SR4 SR3 SR2 SR1 AD1986A D0 Default SR0 0xxxxx Default Default: 0 Default Default ...
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... AD1986A Register Function 0x09 0x0A 0x0B–0x0E 0x0F 0x10–0x1F S [4:0] (RO) Sensed bits (when input sense cycle initiated). This field allows for the reporting of the type of input peripheral/device plugged in the jack. Specified values should be interrogated with the SR [5:0] and OR [1:0] bits for accurate reporting. ...
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... One percent tolerance resistors should be used for all jack presence circuitry to ensure accurate detection. AUDIO JACK STYLES (NC/NO) The jack sense lines on the AD1986A can be programmed for use with normally-open (NO) or normally closed (NC) switch types. Current standard stereo audio jacks have wrap-back pins that are normally closed ...
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... AD1986A MICROPHONE SELECTION/MIXING MIC 1 CENTER LINE IN L MIC 2 LFE LINE DataSheet U .com NID: 0x0F MIC Select: OMS[2:0] 0x74 D10-D08 G DEF=000 (MIC 1/2) 000-MIC 1/2 001-Line In MIC Boost: AC97 01x-C/LFE M20 0x0E D6 DEF=0 100-MIC+C/LFE MGB[1:0] 0x76 D[1:0] DEF=00 101-MIC+Line In MIC Swap: AC97 ...
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... OUTLINE DIMENSIONS 1.00 12° MAX 0.85 0.80 ORDERING GUIDE Model AD1986AJSTZ 1 AD1986AJSTZ-REEL 1 1 AD1986ABSTZ 1 AD1986ABSTZ-REEL AD1986AJCP AD1986AJCP-RL 1 AD1986AJCPZ 1 AD1986AJCPZ- Pb-free part. 4 DataSheet U .com 0.75 1.60 0.60 MAX 0.45 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE VIEW A COPLANARITY VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 4. 48-Lead Low Profile Quad Flat Package [LQFP] ...
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... AD1986A NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 4 DataSheet U .com D05496–0-–4/05(0) Rev Page ...