AD5313 Analog Devices, AD5313 Datasheet
AD5313
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... V to 5.5 V supply, consuming 230 μ Their on-chip output amplifiers allow the outputs to swing rail-to- rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates MHz and is compatible with standard SPI, QSPI™, MICROWIRE™ ...
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... AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20 AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20 AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20 AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20 Applications Information .............................................................. 21 Typical Application Circuit....................................................... 21 Bipolar Operation Using the AD5303/AD5313/AD5323..... 21 Opto-Isolated Interface for Process Control Applications ... 22 Decoding Multiple AD5303/AD5313/AD5323s.................... 22 AD5303/AD5313/AD5323 as a Digitally Programmable Window Detector ....................................................................... 22 Coarse and Fine Adjustment Using the AD5303/AD5313/AD5323 ...
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... V − 0.001 2.5 5 Rev Page AD5303/AD5313/AD5323 unless otherwise noted. MIN MAX Unit Conditions/Comments Bits LSB LSB Guaranteed monotonic by design over all codes Bits LSB LSB Guaranteed monotonic by design over all codes Bits ...
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... See the Terminology section specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V and offset plus gain error must be positive ...
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... AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 2. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET ERROR Rev Page AD5303/AD5313/AD5323 GAIN ERROR PLUS OFFSET ERROR ACTUAL IDEAL DAC CODE Figure 3. Transfer Function with Positive Offset ...
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... AC CHARACTERISTICS kΩ to GND Table 2. Parameter 2 Output Voltage Settling Time AD5303 AD5313 AD5323 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion 1 Guaranteed by design and characterization, not production tested. ...
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... Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications SCLK SYNC DIN* DB15 LDAC LDAC CLR * SEE THE INPUT SHIFT REGISTER SECTION. Figure 5. Serial Interface Timing Diagram AD5303/AD5313/AD5323 2mA 50pF 2mA DB0 t 9 ...
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... AD5303/AD5313/AD5323 ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted. A Table 4. Parameter V to GND DD Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND GND OUT OUT Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (T ...
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... TOP VIEW REF (Not to Scale OUT OUT BUF BUF DCEN Figure 6. Pin Configuration in unbuffered mode and from unbuffered mode and from Rev Page AD5303/AD5313/AD5323 in buffered mode buffered mode. DD ...
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... AD5303/AD5313/AD5323 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measure of the maximum deviation, in LSB, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL error vs. code plot can be seen in Figure 7, Figure 8, and Figure 9. ...
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... CODE Figure 7. AD5303 Typical INL Plot 25° –1 –2 –3 0 200 400 600 CODE Figure 8. AD5313 Typical INL Plot 25° –4 –8 –12 0 1000 2000 CODE Figure 9. AD5323 Typical INL Plot 0.3 0.2 0.1 – ...
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... AD5303/AD5313/AD5323 1.00 0.75 0.50 0.25 MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.50 –0.75 –1. (V) REF Figure 13. AD5303 INL and DNL Error vs REF 0.75 0.50 MAX DNL MAX INL 0.25 0 –0.25 MIN INL MIN DNL –0.50 –0.75 –1.00 – TEMPERATURE (°C) Figure 14 ...
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... CH1 5.0 5.5 Figure 22. Half-Scale Settling (¼ to ¾ Scale Code Change CH1 CH2 +105°C 5 CH1 CH3 4.0 4.5 5.0 Rev Page AD5303/AD5313/AD5323 CLK V OUT CH1 1V, CH2 5V, TIME BASE = 5µs/DIV = 25° OUT CH1 1V, CH2 1V, TIME BASE = 20µs/DIV Figure 23 ...
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... AD5303/AD5313/AD5323 2.50 2.49 2.48 2.47 1µs/DIV Figure 25. AD5323 Major-Code Transition 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY(Hz) Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response) 100k 1M 10M Rev Page 500ns/DIV Figure 27. DAC-to-DAC Crosstalk 0. 25° 0.05 0 –0.05 –0. ...
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... REF V OUT N 2 where the decimal equivalent of the binary code, which is loaded to the DAC register 255 for AD5303 (8 bits 1023 for AD5313 (10 bits 4095 for AD5323 (12 bits the DAC resolution REF REFERENCE BUFFER INPUT DAC ...
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... AD5303/AD5313/AD5323 POWER-ON RESET The AD5303/AD5313/AD5323 are provided with a power-on reset function, so that they power defined state. The power-on state is with output range and the output REF set Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device ...
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... The remaining bits are DAC data bits, starting with the MSB and ending with the LSB. The AD5323 uses all 12 bits of DAC data; the AD5313 uses 10 bits and ignores the 2 LSBs. The AD5303 uses eight bits and ignores the last four bits. The data ...
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... D2 D1 DATA BITS Figure 31. AD5303 Input Shift Register Contents PD1 PD0 DATA BITS Figure 32. AD5313 Input Shift Register Contents PD1 PD0 D11 D10 DATA BITS Figure 33. AD5323 Input Shift Register Contents Rev Page DB0 (LSB) D0 ...
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... POWER-DOWN MODES The AD5303/AD5313/AD5323 have very low power consump- tion, dissipating only 0.7 mW with supply and 1.5 mW with supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word ...
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... Data is transmitted MSB first. To load data to the AD5303/AD5313/ AD5323, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure ...
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... APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT The AD5303/AD5313/AD5323 can be used with a wide range of reference voltages, especially if the reference inputs are con- figured to be unbuffered, in which case the devices offer a full, one-quadrant multiplying capability over a reference range More typically, the AD5303/AD5313/AD5323 may be used with a fixed precision reference voltage ...
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... Figure 43 shows a diagram of a typical setup for decoding multiple AD5303/AD5313/AD5323 devices in a system. ENABLE CODED ADDRESS Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System 10µF 0.1µF AD5303/AD5313/AD5323 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR A digitally programmable upper/lower limit detector using ...
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... COARSE AND FINE ADJUSTMENT USING THE AD5303/AD5313/AD5323 The DACs in the AD5303/AD5313/AD5323 can be paired together to form a coarse and fine adjustment function, as shown in Figure 45. DAC A provides the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments ...
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... The power supply lines of the AD5303/AD5313/AD5323 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast ...
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... AD5313ARU-REEL7 –40°C to +105°C 1 AD5313ARUZ –40°C to +105°C AD5313BRU –40°C to +105°C AD5313BRU-REEL –40°C to +105°C AD5313BRU-REEL7 –40°C to +105°C 1 AD5313BRUZ –40°C to +105°C AD5323ARU –40°C to +105°C AD5323ARU-REEL7 –40°C to +105°C AD5323ARUZ 1 – ...
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... AD5303/AD5313/AD5323 NOTES Rev Page ...
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... NOTES AD5303/AD5313/AD5323 Rev Page ...
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... AD5303/AD5313/AD5323 NOTES ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00472-0-6/07(B) Rev Page ...