AD5317 Analog Devices, AD5317 Datasheet
AD5317
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AD5317 Summary of contents
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... V to 5.5 V supplies and consume 400 μ Their on- chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize versatile 3-wire serial interfaces that operate at clock rates MHz; these parts are compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards ...
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... Microprocessor Interfacing....................................................... 19 Applications..................................................................................... 20 Typical Application Circuit....................................................... 20 Driving V from the Reference Voltage ................................ 20 DD Bipolar Operation....................................................................... 20 Opto-Isolated Interface for Process-Control Applications... 21 Decoding Multiple AD5307/AD5317/AD5327 Devices....... 21 AD5307/AD5317/AD5327 as Digitally Programmable Window Detectors ..................................................................... 21 Daisy Chaining ........................................................................... 22 Power Supply Bypassing and Grounding................................ 22 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 25 8/03—Rev Rev. A Added A Version ...
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... V − V − 0.001 0.001 0.5 0 2.5 2 Rev Page AD5307/AD5317/AD5327 unless otherwise noted. MIN MAX Max Unit Conditions/Comments Bits ±0.625 LSB ±0.25 LSB Guaranteed monotonic by design over all codes Bits ±2.5 LSB ±0.5 LSB Guaranteed monotonic by design ...
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... See the Terminology section specifications tested with the outputs unloaded, unless otherwise noted. 4 Linearity is tested using a reduced code range: AD5307 (Code 8 to Code 255); AD5317 (Code 28 to Code 1023); AD5327 (Code 115 to Code 4095). 5 This corresponds to x codes, where x = deadband voltage/LSB size. 6 Guaranteed by design and characterization ...
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... SCLK falling edge to SYNC rising edge ns min SYNC rising edge to SCLK rising edge ns min SYNC rising edge to LDAC falling edge ) and timed from a voltage level determines maximum SCLK frequency in daisy-chain mode. 13 Rev Page AD5307/AD5317/AD5327 unless otherwise noted. MIN MAX Conditions/Comments REF ...
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... AD5307/AD5317/AD5327 SCLK SYNC DIN DB15 1 LDAC 2 LDAC CLR NOTES 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. SCLK SYNC LDAC DIN DB15 SDO 2mA OUTPUT PIN C L 50pF 2mA I OH Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications ...
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... 0.3 V maximum rating conditions for extended periods may affect DD −0 0.3 V device reliability. DD −40°C to +105°C −65°C to +150°C 150°C (T max − T )/θ 150.4°C/W 220°C 10 sec to 40 sec Rev Page AD5307/AD5317/AD5327 ...
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... Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. SDO CLR 1 16 SYNC LDAC 2 15 AD5307/ AD5317/ SCLK AD5327 DIN 13 ...
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... CODE Figure 6. AD5307 INL 25° –1 –2 –3 0 200 400 600 CODE Figure 7. AD5317 INL 25° –4 –8 –12 0 1000 2000 CODE Figure 8. AD5327 INL 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 ...
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... AD5307/AD5317/AD5327 0. 25° 0.25 0 –0.25 –0. (V) REF Figure 12. AD5307 INL Error and DNL Error vs REF MAX INL 0.3 0.2 MAX DNL 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 – TEMPERATURE (°C) Figure 13. AD5307 INL Error and DNL Error vs. Temperature 1 ...
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... CH1 –40°C CH2 +105°C 4.5 5.0 5 25°C A CH1 CH2 Rev Page AD5307/AD5317/AD5327 T = 25° REF V A OUT SCLK CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change 25° ...
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... AD5307/AD5317/AD5327 350 400 450 500 I (µA) DD Figure 24. I Histogram with and 2.50 2.49 2.48 2.47 1µs/DIV Figure 25. AD5327 Major-Code Transition Glitch Energy 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY (Hz) Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response 550 ...
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... THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output measured in decibels. Rev Page AD5307/AD5317/AD5327 ...
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... AD5307/AD5317/AD5327 TRANSFER FUNCTION VOLTAGE OUTPUT VOLTAGE NEGATIVE OFFSET DAC CODE ERROR ACTUAL IDEAL LOWER DEAD BAND CODES AMPLIFIER FOOTROOM NEGATIVE OFFSET ERROR Figure 29. Transfer Function with Negative Offset OUTPUT POSITIVE OFFSET ERROR DAC CODE Figure 30. Transfer Function with Positive Offset (V Rev Page ...
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... If there is a buffered reference in the circuit (for example, REF192), there is no need to use the on-chip buffers of the AD5307/AD5317/ AD5327. In unbuffered mode, the input impedance is still large at typically 90 kΩ per reference input for kΩ ...
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... Figure 16. The slew rate is 0.7 V/μs, with a half-scale settling time to ±0.5 LSB (at eight bits μs. POWER-ON RESET The AD5307/AD5317/AD5327 are each provided with a power- on reset function so that they power defined state. The power-on state is • ...
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... A1 A0 The AD5327 uses all 12 bits of DAC data; the AD5317 uses 10 bits and ignores the 2 LSBs. The AD5307 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding output and all 1s corresponding to ...
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... LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5307/AD5317/AD5327, the DAC register updates only if the input register has changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk ...
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... The SYNC signal is again derived from a bit- programmable pin on the port. In this case, Port Line P3.3 is used. When data transmitted to the AD5307/AD5317/ AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle ...
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... AD5307/AD5317/AD5327 APPLICATIONS TYPICAL APPLICATION CIRCUIT The AD5307/AD5317/AD5327 can be used with a wide range of reference voltages and offer full, one-quadrant multiplying capability over a reference range of 0. these devices are used with a fixed precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2 ...
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... ADDRESS AD5307/AD5317/AD5327 AS DIGITALLY PROGRAMMABLE WINDOW DETECTORS 0.1µF 10µF A digitally programmable upper/lower limit detector using two of the DACs in the AD5307/AD5317/AD5327 is shown in Figure 45. The upper and lower limits for the test are loaded to DAC and DAC B, which, in turn, set the limits on the CMP04. If the ...
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... The printed circuit board on which the AD5307/AD5317/AD5327 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5307/AD5317/AD5327 are in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one ...
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... Rev Page AD5307/AD5317/AD5327 Settling Time (μs) Package 4 SOT-23, MSOP 6 SOT-23, MSOP 8 SOT-23, MSOP 6 SOT-23, MSOP 7 SOT-23, MSOP 8 SOT-23, MSOP 6 MSOP 7 MSOP 8 MSOP 6 TSSOP 7 TSSOP 8 TSSOP ...
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... AD5307/AD5317/AD5327 OUTLINE DIMENSIONS 0.15 0.05 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0.65 0° 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev Page 0.75 0.60 0.45 ...
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... AD5317ARUZ −40°C to +105°C AD5317BRU −40°C to +105°C AD5317BRU-REEL −40°C to +105°C AD5317BRU-REEL7 −40°C to +105°C AD5317BRUZ 1 −40°C to +105°C 1 AD5317BRUZ-REEL −40°C to +105°C 1 AD5317BRUZ-REEL7 −40°C to +105°C AD5327ARU −40°C to +105°C AD5327ARU-REEL7 − ...
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... AD5307/AD5317/AD5327 NOTES Rev Page ...
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... NOTES AD5307/AD5317/AD5327 Rev Page ...
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... AD5307/AD5317/AD5327 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02067–0–3/06(C) Rev Page ...