AD5641 Analog Devices, AD5641 Datasheet

no-image

AD5641

Manufacturer Part Number
AD5641
Description
2.7 V to 5.5 V,
Manufacturer
Analog Devices
Datasheet

Specifications of AD5641

Resolution (bits)
14bit
Dac Update Rate
1.7MSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5641BKSZ-500RL7
Manufacturer:
ADI
Quantity:
11 554
Data Sheet
FEATURES
6-lead LFCSP and SC70 packages
Micropower operation: 100 µA maximum at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
B version: ±4 LSB INL
A version: ±16 LSB INL
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5641, a member of the nanoDAC® family, is a single,
14-bit, buffered, voltage-out DAC that operates from a single
2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in tiny LFCSP and SC70 packages. Its on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5641 uses a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
reference for AD5641 is derived from the power supply inputs
and, therefore, gives the widest dynamic output range. The part
incorporates a power-on reset circuit, which ensures that the
DAC output powers up to 0 V and remains there until a valid
write to the device takes place.
The AD5641 contains a power-down feature that reduces
current consumption typically to 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2.7 V to 5.5 V, <100 µA, 14-Bit nanoDAC,
SPI Interface in LFCSP and SC70
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Table 1. Related Devices
Part Number
AD5601
AD5611
AD5621
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
SYNC
Available in space-saving 6-lead LFCSP and SC70
packages.
Low power, single-supply operation. The AD5641 operates
from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
Reference derived from the power supply.
High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.
Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V.
Power-on reset with brownout detection.
CONTROL
POWER-ON
LOGIC
REGISTER
INPUT
RESET
SCLK SDIN
DAC
FUNCTIONAL BLOCK DIAGRAM
©2005–2012 Analog Devices, Inc. All rights reserved.
Description
2.7 V to 5.5 V, <100 µA, 8-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
2.7 V to 5.5 V, <100 µA, 10-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
2.7 V to 5.5 V, <100 µA, 12-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
REF(+)
V
DD
14-BIT
DAC
CONTROL LOGIC
POWER-DOWN
GND
Figure 1.
OUTPUT
BUFFER
AD5641
AD5641
www.analog.com
RESISTOR
NETWORK
V
OUT

Related parts for AD5641

AD5641 Summary of contents

Page 1

... Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5641, a member of the nanoDAC® family single, 14-bit, buffered, voltage-out DAC that operates from a single 2 5.5 V supply, typically consuming 75 µ The part comes in tiny LFCSP and SC70 packages. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved ...

Page 2

... Power-On Reset .......................................................................... 14 Power-Down Modes .................................................................. 14 Microprocessor Interfacing ....................................................... 15 Applications ..................................................................................... 16 Choosing a Reference as Power Supply for the AD5641....... 16 Bipolar Operation Using the AD5641 ..................................... 16 Using the AD5641 with a Galvanically Isolated Interface .... 17 Power Supply Bypassing and Grounding ................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19 3/05—Rev Rev. A Changes to Timing Characteristics ................................................. 4 Changes to Absolute Maximum Ratings ...

Page 3

... Rev Page AD5641 to T MIN Unit Test Conditions/Comments Bits LSB LSB Guaranteed monotonic by design mV All 0s loaded to DAC register mV mV All 1s loaded to DAC register % of FSR µV/°C ppm of FSR/°C V µs Code ¼ scale to ¾ scale, to ±1 LSB V/µ ...

Page 4

... AD5641 TIMING CHARACTERISTICS 5.5 V; all specifications T DD Table 3. Parameter Limit 4 All input signals are specified with ns/V (10 Maximum SCLK frequency is 30 MHz. ...

Page 5

... 0 maximum rating conditions for extended periods may affect –0 0 device reliability. –40°C to +125°C –65°C to +160°C ESD CAUTION 150°C 433.34°C/W 149.47°C/W 95°C/W 260°C 20 sec to 40 sec 2.0 kV Rev Page AD5641 ...

Page 6

... SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input Power Supply Input. The AD5641 can be operated from 2 5 GND GND Ground Reference Point for All Circuitry on the AD5641. ...

Page 7

... MIN TUE ERROR @ REF –14 –40 – 100 TEMPERATURE (° 25° MAX TUE ERROR –5 MIN TUE ERROR –10 –15 2.7 3.2 3.7 4.2 4.7 SUPPLY (V) Figure 10. Total Unadjusted Error (TUE) vs. Supply at 25°C AD5641 14256 = 5V 120 140 5.2 ...

Page 8

... AD5641 0.0025 0.0020 0.0015 ZERO-CODE ERROR @ V DD 0.0010 0.0005 ZERO-CODE ERROR @ V FULL-SCALE ERROR @ V 0 –0.0005 –0.0010 FULL-SCALE ERROR @ –0.0015 –0.0020 –0.0025 –40 – TEMPERATURE (°C) Figure 11. Zero-Code/Full-Scale Error vs. Temperature (3 V/5 V) 0.0020 T = 25° ...

Page 9

... DAC LOADED WITH FULL-SCALE CODE –0.4 –0.6 –15 –10 – (mA) Figure 21. Sink and Source Capability 2000 4000 6000 8000 10000 12000 14000 16000 DIGITAL INPUT CODE Figure 22. Supply Current vs. Digital Input Code AD5641 5 ...

Page 10

... AD5641 CH1 = SCLK CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV Figure 23. Full-Scale Settling Time CH1 = SCLK CH2 = V OUT CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV Figure 24. Midscale Settling Time 25°C A CH1 V CH2 CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV Figure 25 ...

Page 11

... Rev Page 25°C A ZERO SCALE MIDSCALE FULL SCALE 1000 10000 FREQUENCY (Hz) Figure 31. Noise Spectral Density T = 25°C SCLK/SDIN A INCREASING SCLK/SDIN DECREASING SCLK/SDIN INCREASING SCLK/SDIN DECREASING (V) LOGIC Figure 32. SCLK/SDIN vs. Logic Voltage AD5641 100000 6 ...

Page 12

... DAC register. Ideally, the output should The zero-code error is always positive in the AD5641 because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV ...

Page 13

... Figure 21. The slew rate is 0.5 V/μs, with a midscale settling time of 8 μs with the output loaded. SERIAL INTERFACE V OUT The AD5641 has a 3-wire serial interface ( SYNC , SCLK, and SDIN) that is compatible with SPI, QSPI, and MICROWIRE OUTPUT AMPLIFIER interface standards, as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence ...

Page 14

... SYNC HIGH BEFORE 16 TH FALLING EDGE POWER-ON RESET The AD5641 contains a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with 0s and the output voltage remains there until a valid write sequence is made to the DAC. This is useful in applica- tions in which it is important to know the state of the DAC output while the process of powering up ...

Page 15

... Data is transmitted MSB first. To load data to the AD5641, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure ...

Page 16

... AD5641 APPLICATIONS CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5641 The AD5641 comes in tiny LFCSP and SC70 packages with less than 100 μA supply current. Because of this, the choice of refer- ence depends on the application requirement. For space-saving applications, the ADR02 is available in an SC70 package and has excellent drift at 9 ppm/° ...

Page 17

... The printed circuit board containing the AD5641 should have separate analog and digital sections, each having its own area of the board. If the AD5641 system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5641 ...

Page 18

... AD5641 OUTLINE DIMENSIONS 0.10 MAX PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 2.20 2.00 1.80 2.40 1. 2.10 1. 1.80 1.15 PIN 1 0.65 BSC 1.30 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.30 SEATING 0.15 PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 46. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 2.10 1.30 2.00 1.90 4 3.10 EXPOSED PAD 3.00 2.90 0.45 0.40 0.35 3 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF ...

Page 19

... AD5641AKSZ-REEL7 –40°C to +125°C AD5641AKSZ-500RL7 –40°C to +125°C AD5641ACPZ-REEL7 –40°C to +125°C AD5641BKSZ-REEL7 –40°C to +125°C AD5641BKSZ-500RL7 –40°C to +125° RoHS Compliant Part. 1 Description Package Description ±16 LSB INL 6-Lead Thin Shrink Small Outline Transistor Package [SC70] ± ...

Page 20

... AD5641 NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04611-0-2/12(D) Rev Page Data Sheet ...

Related keywords