AD652 Analog Devices, AD652 Datasheet
AD652
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AD652 Summary of contents
Page 1
... The AD652 includes a buffered, accurate 5 V reference which is available to the user. 4. The clock input of the AD652 is TTL and CMOS compat- ible and can also be driven by sources referred to the negative power supply. The flexible open-collector output stage pro- vides sufficient current sinking capability for TTL and CMOS logic, as well as for optical couplers and pulse transformers ...
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... S 0.5 5 – – 1.2 0.8 2 – –2– AD652KP/BQ Min Typ Max Units ± 0.25 ± 0.5 % ± 0.25 0.5 % ± 0.25 0.75 % ± 15 ± 25 ppm/°C ± ppm/°C ± ppm/°C ± ppm/°C 0.001 ...
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... GAIN TEMPERATURE COEFFICIENT—The gain tempera- ture coefficient is the rate of change in full-scale frequency as a function of the temperature from +25° –3– AD652 AD652KP/BQ Min Typ Max Units 0.4 V ...
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... Cerdip (Q-16) Cerdip (Q-16) Cerdip (Q-16) Figure 1a. Cerdip Pin Configuration The pinouts of the AD652 SVFC are shown in Figure 1. A block diagram of the device configured as a SVFC, along with various system waveforms, is shown in Figure 2. Figure 1b. PLCC Pin Configuration Figure 2 shows the typical up-and-down ramp integrator output of a charge-balance VFC ...
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... Figure 2. AD652 Block Diagram and System Waveforms Referring to Figure 2, it can be seen that the period between output pulses is constrained exact multiple of the clock period ...
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... The cerdip packaged AD652 accepts either 0.5 mA full-scale input signal. The temperature drift of the AD652 is specified for input range using the internal 20 kΩ resistor current input is used, the gain drift will be degraded by a maximum of 100 ppm/°C (the TC of the 20 kΩ ...
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... ZERO Figure 9. GAIN AND OFFSET CALIBRATION The gain error of the AD652 is laser trimmed to within ± 0.5%. If higher accuracy is required, the internal 20 kΩ resistor must be shunted with a 2 MΩ resistor to produce a parallel equivalent which is 1% lower in value than the nominal 20 kΩ. Full-scale Figure 10a ...
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... Figure 11 shows a plot of the typical gain error changes vs. the clock input frequency, normalized to 100 kHz. If after using the AD652 with a full-scale clock frequency of 100 kHz it is decided to reduce the necessary gat- ing time by increasing the clock frequency, this plot shows the typical gain changes normalized to the original 100 kHz gain ...
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... V–5 V)/500 µ kΩ). REV. B Figure 16 shows the negative voltage input configuration for use and (+V of the AD652 in the single supply mode. In this mode the signal S S source is driving the “+” input of the op amp which requires only 20 nA (typical), rather than the 0 ...
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... Such ringing can also couple interference into sensi- tive analog circuits. The best solution to these problems is proper bypassing of the logic supply at the AD652 package µ µF tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to the digital ground, Pin 12 ...
Page 11
... The one-shot in the AD652 sets the pulse width of the frequency output pulses to be slightly shorter than one quarter of the clock period. Synchronization is achieved by applying one of the four available phases to a fixed TTL one-shot (’ ...
Page 12
... The RC lag network on the input of the one-shot provides a slight delay between the rising edge of the clock and the sync pulse in order to match the 150 ns delay of the AD652 between the rising edge of the clock and the output pulse. Transmitter The multiplex signal can be transmitted in any manner suitable to the task at hand ...
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... These frequency signals can be counted as a ratio relative to the reconstructed clock not even necessary for the transmitter to be crystal controlled as shown here. Figure 23. SVFC Demultiplexers Figure 25. Demultiplexer Waveforms –13– AD652 ...
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... The circuit shown in Figure 27 runs off a single 5 volt power supply and provides a self- contained, completely isolated analog measurement system. The power for the AD652 SVFC is provided by a chopper and a transformer, and is regulated to ± 15 volts. Both the chopper frequency and the AD652 clock frequency are 125 kHz, with the clock signal being relayed to the SVFC through the transformer ...
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... Digits 20000 16 Bits 16 Bits DELTA MODULATOR The circuit of Figure 29 shows the AD652 configured as a delta modulator. A reference voltage is applied to the input of the integrator (Pin 7), which sets the steady state output frequency at one-half of the AD652 full-scale frequency (1/4 of the clock frequency input signal is applied to the com- parator (Pin 15), the output of the integrator attempts to track this signal ...
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... If the signal is unipolar, the reference input of the AD625 (Pin 7) is simply grounded. If the bridge has a bipolar output, however, the AD652 reference can be tied to Pin 7, thereby, converting a ± 5 volt signal (after gain) into a 0 volt to +10 volt input for the SVFC. ...