AD7467 Analog Devices, AD7467 Datasheet
AD7467
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AD7467 Summary of contents
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... Medical instruments Remote data acquisition Isolated data acquisition GENERAL DESCRIPTION 1 The AD7466/AD7467/AD7468 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 1 3.6 V power supply and feature throughput rates up to 200 kSPS with low power dissipation. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz ...
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... Circuit Information.................................................................... 17 Converter Operation.................................................................. 17 ADC Transfer Function............................................................. 17 Typical Connection Diagram ................................................... 17 Analog Input ............................................................................... 18 Digital Inputs .............................................................................. 18 Normal Mode.............................................................................. 19 Power Consumption .................................................................. 20 Serial Interface ................................................................................ 22 Microprocessor Interfacing....................................................... 23 Application Hints ........................................................................... 25 Grounding and Layout .............................................................. 25 Evaluating the Performance of the AD7466 and AD7467.... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 Rev Page ...
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... DD 0.8 V max 2.7 V ≤ V ±1 μA max Typically 20 nA, V ±1 μA typ 10 pF max Sample tested at 25°C to ensure compliance Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 30 kHz sine wave IN ≤ see the Terminology section DD ≤ ≤ ...
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... AD7466/AD7467/AD7468 Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode ...
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... Sample tested at 25°C to ensure compliance Straight (natural) binary 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz 275 kSPS max See the Serial Interface section Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 1 kHz sine wave DD IN ≤ 3 ≤ ...
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... AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 1.6/3.6 V min/max Digital inputs = 210 μA max 170 μA max 140 μA max ...
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... Sample tested at 25°C to ensure compliance Straight (natural) binary 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz 320 kSPS max See the Serial Interface section Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 1 kHz sine wave DD IN ≤ 3 ≤ ...
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... AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 1.6/3.6 V min/max Digital inputs = 190 μA max 155 μA max 120 μA max ...
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... OL TO OUTPUT PIN C L 50pF 200μ Figure 2. Load Circuit for Digital Output Timing Specifications Rev Page AD7466/AD7467/AD7468 at which specifications are guaranteed. SCLK at which specifications are guaranteed. at which specifications are guaranteed. = 1.6 V and f = 3.4 MHz, t has to be 192 ns DD SCLK ...
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... AD7466/AD7467/AD7468 TIMING EXAMPLES Figure 3 shows some of the timing parameters from Table 4 in the Timing Specifications section. Timing Example 1 As shown in Figure 3.4 MHz and a throughput of SCLK 100 kSPS gives a cycle time CONVERT Assuming 15(1/f DD CONVERT 2 4.41 μs = 4.46 μs, and maximum, then t ...
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... 0 device reliability. −0 −0 0 ±10 mA ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 229.6°C/W 91.99°C/W 205.9°C/W 43.74°C/W 215°C 220°C 3.5 kV Rev Page AD7466/AD7467/AD7468 ...
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... AD7466 consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10 bits of conversion data, provided MSB first. The data stream from the AD7468 consists of four leading zeros followed by the 8 bits of conversion data, provided MSB first ...
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... TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES Figure 6, Figure 7, and Figure 8 show typical FFT plots for the AD7466, AD7467, and AD7468, respectively 100 kSPS sample rate and a 30 kHz input tone. Figure 9 shows the signal-to-noise and distortion ratio performance vs. input frequency for various supply voltages while sampling at 100 kSPS with an SCLK frequency of 3 ...
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... AD7466/AD7467/AD7468 5 –5 –15 –25 –35 –45 –55 –65 –75 –85 – FREQUENCY (kHz) Figure 8. AD7468 Dynamic Performance at 100 kSPS –65 –66 –67 –68 – –70 –71 – 3. –73 10 INPUT FREQUENCY (kHz) Figure 9. AD7466 SINAD vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages – ...
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... TEMP = +25°C 1.0 0.8 0.6 0.4 0.2 0 3.2 3.4 3.6 3.8 Figure 18. AD7466 Power Consumption vs. Throughput Rate, SCLK 3.4 MHz f = 50kSPS SAMPLE 3.2 3.4 3.6 3.8 Rev Page AD7466/AD7467/AD7468 TEMP = +85 ° C TEMP = +25 ° C TEMP = –40 ° C 1.5 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) Figure 17. Shutdown Current vs. Supply Voltage TEMP = 25 ° 100 150 200 THROUGHPUT (kSPS ...
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... The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7466/ AD7467/AD7468, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ...
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... ADC output code. Figure 21 shows the ADC transfer function ADC TRANSFER FUNCTION The output coding of the AD7466/AD7467/AD7468 is straight binary. The designed code transitions occur at successive integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size for the devices is as follows external refer- ...
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... V or 2.5 V (for example, 5 V). The REF19x outputs a steady voltage to the AD7466/AD7467/AD7468. If the low dropout REF192 is used when the AD7466 is converting at a rate of 100 kSPS, the REF192 needs to supply a maximum of 240 μA to the AD7466. ...
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... The AD7466 automatically enters power-down mode on the 16th SCLK falling edge. For the AD7467, 14 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7467 automatically enters power-down mode on the 14th SCLK falling edge ...
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... The AD7466/AD7467/AD7468 automatically enter power- down mode at the end of each conversion brought high before the conversion is finished. When the AD7466/AD7467/AD7468 are in power-down mode, all the analog circuitry is powered down and the current con- sumption is typically 8 nA. To achieve the lowest power dissipation, there are some considerations the user should keep in mind ...
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... V= (87.42 + 0.053) μA × 1 157.4 μW = 0.157 mW Power Consumption B = ((4.7/20) × 186 μA + (15.3/20) × 100 nA) × 1 (43.7 + 0.076) μA × 1 78.79 μW = 0.078 mW It can be concluded that for a fixed SCLK frequency, the average power consumption drops as the throughput rate decreases. Rev Page AD7466/AD7467/AD7468 = 1 1 ...
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... Figure 29. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7466. For the AD7467, the 14th SCLK falling edge causes the SDATA line to go back into three-state, and the part enters power-down. If the rising edge of CS occurs before 14 SCLKs elapse, the con- version terminates, the SDATA line goes back into three-state, and the AD7467 enters power-down ...
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... AD7468 where 14 and 12 bits are required, the FO bit also would be set bits. In these cases, the user should keep in mind that the last 2 bits and 4 bits for the AD7467 and AD7468, respectively, are invalid data as the SDATA line goes back into three-state on the 14th and 12th SCLK falling edge. ...
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... AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not offer the option for a 14-bit word length, so the AD7467 word length is set bits like the AD7466 word length. In this case, the user should keep in mind that the last two bits are invalid data because the SDATA goes back into three-state on the 14th SCLK falling edge ...
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... Analog Devices evaluation boards ending in the CB designator. The software allows the user to perform ac tests (fast Fourier transform) and dc tests (histogram of codes) on the AD7466 and AD7467. See the data sheet in the evaluation board package for more information. Rev Page and ...
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... AD7466/AD7467/AD7468 OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 35. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 2. PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 8° 0.15 0.38 0.23 0° 0.00 0.22 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 36 ...
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... AD7467BRTZ-REEL7 −40°C to +85°C 2 AD7467BRTZ-R2 −40°C to +85°C AD7467BRM −40°C to +85°C AD7467BRM-REEL −40°C to +85°C AD7467BRM-REEL7 −40°C to +85°C 2 AD7467BRMZ −40°C to +85°C AD7468BRT-REEL −40°C to +85°C AD7468BRT-REEL7 −40°C to +85°C AD7468BRT-R2 − ...
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... AD7466/AD7467/AD7468 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02643-0-5/07(C) Rev Page ...