AD7478 Analog Devices, AD7478 Datasheet
AD7478
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AD7478 Summary of contents
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... DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts. The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from V allows the widest dynamic input range to the ADC ...
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... Ordering Guide .......................................................................... 22 3/04—Rev Rev. D Added U.S. Patent Number .............................................................. 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section .............................................................................. 16 2/03—Rev Rev. C Changes to General Description ..................................................... 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to Ordering Guide ............................................................. 6 Changes to Typical Connection Diagram section ..................... 10 Changes to Figure 8 caption ...
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... V − 0.2 V − 0.2 V − 0 0.4 0.4 0.4 ±10 ±10 ± Straight (Natural) Binary Rev Page AD7476/AD7477/AD7478 = 2. 5. 1,2 Unit Test Conditions/Comments f = 100 kHz sine wave IN dB min B version 2 5. min T = 25° typ dB min B version 2 5. typ ...
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... AD7476/AD7477/AD7478 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 7 Normal Mode (Operational) Full Power-Down 1 Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C. ...
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... DD DD 0.4 0.4 ±10 ± Straight (Natural) Binary 800 800 400 400 1 1 Rev Page AD7476/AD7477/AD7478 Unit Test Conditions/Comments f = 100 kHz sine wave SAMPLE dB min dB max dB max dB typ fa = 103.5 kHz 113.5 kHz dB typ fa = 103.5 kHz 113.5 kHz ns typ ps typ MHz typ ...
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... AD7476/AD7477/AD7478 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode 5 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from V = 2.0 V, with input high voltage, V ...
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... AD7478 SPECIFICATIONS MHz SCLK Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) 3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution ...
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... DD 2 Guaranteed by characterization. All input signals are specified with (10 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0 2.0 V. ...
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... maximum rating conditions for extended periods may affect −0 0 device reliability. 1 ±10 mA –40°C to +85°C −55°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 235 (0/+5)°C 255 (0/+5)°C 3.5 kV Rev Page AD7476/AD7477/AD7478 ...
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... MSB first. The data stream from the AD7477 consists of four leading zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first. The data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion data, followed by four trailing zeros, which is provided MSB first. ...
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... THD = –75.22dB SFDR = –67.78dB –30 –40 –50 –60 –70 –80 – 100 150 200 250 300 350 FREQUENCY (kHz) Figure 7. AD7478 Dynamic Performance at 1 MSPS –66 SCLK = 20MHz V = 2.35V DD –67 –68 –69 – 5.25V DD –71 – –73 ...
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... LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. For the AD7478, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition ...
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... AD7476/AD7477 is shown in Figure 12. For the AD7478, designed code transitions occur midway between successive integer LSB values, such as 1 LSB, 2 LSB, and so on. The LSB size for the AD7478 is V transfer characteristic for the AD7478 is shown in Figure 13. 111 ... 111 111 ... 110 111 ...
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... The REF19x outputs a steady voltage to the AD7476/ AD7477/AD7478. If the low dropout REF193 is used, the current it typically needs to supply to the AD7476/AD7477/ AD7478 is 1 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 needs to supply a maximum of 1 the AD7476/AD7477/AD7478. The load regulation of the REF193 is typically 10 ppm/mA (REF193, V results in an error of 16 ppm (48 μ ...
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... Figure 18. THD vs. Analog Input Frequency, f Digital Input 605kSPS S The digital input applied to the AD7476/AD7477/AD7478 is not limited by the maximum ratings that limit the analog input. Instead, the digital input applied can and is not f = 200kHz IN restricted by the V example, if the AD7476/AD7477/AD7478 are operated with then 5 V logic levels can be used on the digital input ...
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... ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7476/AD7477/ AD7478 is in power-down mode, all analog circuitry is powered down. To enter power-down, the conversion process must be interrupted by bringing CS high any time after the second ...
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... CS . When running at 1 MSPS throughput rate, the AD7476/AD7477/ AD7478 powers up and acquires a signal within ±0.5 LSB in one dummy cycle, such as 1 μs. When powering up from the power-down mode with a dummy ...
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... Therefore, the first rising edge of SCLK after the CS falling edge provides the second leading zero. The 15th CS occurs before rising SCLK edge has DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. t ...
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... WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode on the AD7476/AD7477/ AD7478, the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. Note that for signal process- ing applications imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling ...
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... SC2 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. Interfacing to the DSP56xxx AD7476/AD7477/AD7478 to MC68HC16 Interface The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR = 1), the clock polarity bit (CPOL and the clock phase bit (CPHA The SPI is configured by writing to the SPI Control Register (SPCR). For more information on the MC68HC16, check with Motorola for the related documentation ...
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... OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 30. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev Page AD7476/AD7477/AD7478 10° 0.60 4° 0.45 0° 0.30 ...
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... AD7477SRTZ-REEL −55°C to +125°C 3 AD7478ARTZ-500RL7 −40°C to +85°C 3 AD7478ARTZ-REEL −40°C to +85°C 3 AD7478ARTZ-REEL7 −40°C to +85°C 3 AD7478SRTZ-REEL7 −55°C to +125°C AD7478WARTZ-RL7 3, 4 −40°C to +85° EVAL-AD7476CBZ 3, 6 EVAL-AD7477CBZ 7 EVAL-CONTROL BRD2 1 Linearity error refers to integral linearity error. ...
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... NOTES AD7476/AD7477/AD7478 Rev Page ...
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... AD7476/AD7477/AD7478 NOTES ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01024-0-1/09(F) Rev Page ...