AD7663AST Analog Devices Inc, AD7663AST Datasheet

IC ADC 16BIT 250KSPS 48-LQFP

AD7663AST

Manufacturer Part Number
AD7663AST
Description
IC ADC 16BIT 250KSPS 48-LQFP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of AD7663AST

Rohs Status
RoHS non-compliant
Number Of Bits
16
Sampling Rate (per Second)
250k
Data Interface
Serial, Parallel
Number Of Converters
1
Power Dissipation (max)
41mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
For Use With
EVAL-AD7663CBZ - BOARD EVALUATION FOR AD7663

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a
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
GENERAL DESCRIPTION
The AD7663 is a 16-bit, 250 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. It contains a high speed 16-bit sampling ADC, a resistor
input scaler that allows various input ranges, an internal conver-
sion clock, error correction circuits, and both serial and parallel
system interface ports.
The AD7663 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP and a tiny
48-lead LFCSP with operation specified from –40°C to +85°C.
*Patent pending
FEATURES
Throughput: 250 kSPS
INL:
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 100 kHz
THD: –100 dB Typ @ 100 kHz
Analog Input Voltage Ranges
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI
Single 5 V Supply Operation
Power Dissipation
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP)
Pin-to-Pin Compatible with the AD7660/AD7664/AD7665
APPLICATIONS
Data Acquisition
Motor Control
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
Bipolar:
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
35 mW Typical
15 W @ 100 SPS
®
/QSPI™/MICROWIRE™/DSP Compatible
3 LSB Max ( 0.0046% of Full Scale)
10 V,
5 V,
2.5 V
PRODUCT HIGHLIGHTS
1. Fast Throughput
2. Single-Supply Operation
3. Superior INL
4. Serial or Parallel Interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
IND(4R)
INC(4R)
INB(2R)
RESET
INGND
INA(R)
The AD7663 is a 250 kSPS charge redistribution, 16-bit
SAR ADC with various bipolar and unipolar input ranges.
The AD7663 operates from a single 5 V supply and dissipates
only 35 mW typical. Its power dissipation decreases with
the throughput to, for instance, only 15 µW at a 100 SPS
throughput.
It consumes 7 µW maximum when in power-down.
The AD7663 has a maximum integral nonlinearity of 3 LSB
with no missing 16-bit code.
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.
Type/kSPS
Pseudo
Differential
True Bipolar
True Differential
18-Bit
Simultaneous/
Multichannel
PD
16-Bit, 250 kSPS CMOS ADC
AVDD AGND REF REFGND
4R
4R
2R
R
CALIBRATION CIRCUITRY
FUNCTIONAL BLOCK DIAGRAM
CONTROL LOGIC AND
SWITCHED
CAP DAC
CNVST
© 2003 Analog Devices, Inc. All rights reserved.
PulSAR Selection
100–250
AD7660
AD7663
AD7675
AD7678
CLOCK
AD7663
INTERFACE
PARALLEL
DVDD
SERIAL
500–570
AD7650
AD7664
AD7665
AD7679
AD7654
AD7676
PORT
AD7663
DGND
16
www.analog.com
800–1000
AD7671
AD7677
AD7674
AD7655
OVDD
OGND
SER/PAR
BUSY
D[15:0]
CS
RD
OB/2C
BYTESWAP
*

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AD7663AST Summary of contents

Page 1

FEATURES Throughput: 250 kSPS INL: 3 LSB Max ( 0.0046% of Full Scale) 16-Bit Resolution with No Missing Codes S/(N+D Typ @ 100 kHz THD: –100 dB Typ @ 100 kHz Analog Input Voltage Ranges Bipolar: 10 ...

Page 2

AD7663–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise 2 Bipolar Zero Error , MIN ...

Page 3

Parameter 8 TEMPERATURE RANGE Specified Performance NOTES 1 LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the ...

Page 4

AD7663 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 17 and 18 (Master Serial Interface Modes) CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert CNVST ...

Page 5

... See Analog Inputs section. Specification is for device in free air: 48-Lead LQFP Specification is for device in free air: 48-Lead LFCSP Model Temperature Range AD7663AST –40°C to +85°C AD7663ASTRL –40°C to +85°C AD7663ACP – +85 C AD7663ACPRL – + EVAL-AD7663CB 2 EVAL-CONTROL BRD2 NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes ...

Page 6

AD7663 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally Connect. 44–48 4 BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, ...

Page 7

Pin No. Mnemonic Type Description 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is ...

Page 8

AD7663 DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB ...

Page 9

CODE TPC 1. Integral Nonlinearity vs. Code 0.3 0.6 0.9 1.2 1.5 ...

Page 10

AD7663 100 95 SNR 90 SINAD FREQUENCY – kHz TPC 7. SNR, S/(N+D), and ENOB vs. Frequency –80 –70 –60 –50 –40 –30 INPUT LEVEL – dB TPC 8. SNR ...

Page 11

SAMPLING RATE – SPS TPC 13. Operating Currents vs. Sample Rate 500 450 400 350 300 250 200 150 100 50 0 –55 –35 – ...

Page 12

AD7663 4R IND REF 4R REFGND INC 2R INB R INA INGND 111...111 111...110 111...101 000...010 000...001 000...000 –FS – LSB –FS + 0.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function Description 1 Full-Scale Range ±10 ...

Page 13

ANALOG SUPPLY (5V ADR421 2.5V REF 1M + NOTE 1 C 50k REF NOTE 2 100nF NOTE 100nF AD8031 NOTE NOTE 5 U1 ANALOG + INPUT 2.7nF ( ...

Page 14

AD7663 FREQUENCY – kHz Figure 7. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the AD7663 behaves like a one-pole RC filter consisting of the ...

Page 15

Voltage Reference Input The AD7663 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7663 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling between ...

Page 16

AD7663 100k 10k 1k 100 100 1k SAMPLING RATE – SPS Figure 10. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion process. The AD7663 is controlled ...

Page 17

PARALLEL INTERFACE The AD7663 is configured to use the parallel interface when the SER/PAR is held LOW. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, ...

Page 18

AD7663 CS CNVST BUSY t 29 SYNC t 14 SCLK t 15 SDOUT t 16 Figure 17. Master Serial Data Timing for Reading (Read after Convert) CS, RD CNVST BUSY t 17 SYNC ...

Page 19

CS BUSY SCLK t 31 SDOUT t 16 SDIN t 33 Figure 19. Slave Serial Data Timing for Reading (Read after Convert) SLAVE SERIAL INTERFACE External Clock The AD7663 is configured to accept an externally supplied serial data clock on ...

Page 20

AD7663 CS CNVST BUSY t 3 SCLK SDOUT t 16 Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion Figure 21 shows the detailed timing diagrams of ...

Page 21

Because the Serial Port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the Serial Port is properly synchronized to this clock during ...

Page 22

AD7663 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown ...

Page 23

Revision History Location 4/03—Data Sheet changed from REV REV. B. Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . ...

Page 24

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