AD7701 Analog Devices, AD7701 Datasheet
AD7701
Specifications of AD7701
Available stocks
Related parts for AD7701
AD7701 Summary of contents
Page 1
... A flexible synchronous/asynchronous interface allows the AD7701 to interface directly to UARTs or to the serial ports of industry-standard microcontrollers. 5. Low operating power consumption and an ultralow power standby mode make the AD7701 ideal for loop-powered remote sensing applications, or battery-powered portable instruments ...
Page 2
... AD7701–SPECIFICATIONS Bipolar Mode: MODE = + Source Resistance = 1k IN Parameter A, S Version STATIC PERFORMANCE Resolution 16 Integral Nonlinearity MIN MAX ± 0.003 Differential Nonlinearity ± 0.125 MIN MAX ± 0.5 ± 0.13 3 Positive Full-Scale Error ± 0.5 ± 1.2 (± 2.3 S Version) 4 Full-Scale Drift ± 0.25 ...
Page 3
... T Version) ) such that the Unipolar mode can mimic Bipolar mode operation. REF –3– AD7701 Unit Test Conditions/Comments V min/V max V min/V max V min/V max V min/V max V min mA max Typically max Typically max Typically max Typically 0 ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7701 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... SDATA REV. E PIN FUNCTION DESCRIPTIONS Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the Asynchronous Communications (AC) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes, each with one start bit and two stop bits. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected ...
Page 6
... See Figures CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7701 is production tested with ...
Page 7
... This is the amount of overhead available to handle voltages below –V without overloading the analog modulator or overflowing REF the digital filter. Note that the analog input will accept negative voltage peaks even in the Unipolar mode. The overhead is expressed in millivolts. –7– AD7701 CLKIN t 3 SLEEP Figure 2b. SLEEP Mode Timing DRDY CS ...
Page 8
... AD7701 can accept and still accu- REF rately calibrate offset. Full-Scale Calibration Range This is the range of voltages that the AD7701 can accept in the system calibration mode and still correctly calibrate full scale. Input Span In system calibration schemes, two voltages applied in sequence to the AD7701’ ...
Page 9
... DIGITAL FILTERING The AD7701’s digital filter behaves like an analog filter, with a few minor differences. First, since digital filtering occurs after the analog-to-digital conversion, it can remove noise injected during the conversion process ...
Page 10
... AD7701 The output settling of the AD7701 in response to a step input change is shown in Figure 12. The Gaussian response has fast settling with no overshoot, and the worst-case settling time to ± 0.0007% (± 0.5 LSB) is 125 ms with a 4.096 MHz master clock frequency. 100 TIME – ...
Page 11
... INPUT SIGNAL CONDITIONING Reference voltages from may be used with the AD7701 with little degradation in performance. Input ranges that cannot be accommodated by this range of reference voltages may be achieved by input signal conditioning. This may take the form of gain to accommodate a smaller signal range, or passive attenua- tion to reduce a larger input voltage range ...
Page 12
... Figure 16. Typical Connections for System Calibration FSE A typical system calibration scheme is shown in Figure 16. In normal operation, the analog signal is fed to the AD7701 via an analog multiplexer. When the system calibrated, A first switched to the system REF LO via the multiplexer and CAL is strobed high, with SC1 and SC2 both high. A switched to the system REF HI and CAL is strobed, with SC1 low and SC2 high ...
Page 13
... System Offset *DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7701 has settled to the analog input. In all other modes, DRDY falls as the device begins to settle. between the multiplexer and the AD7701 is removed. Op amps and other signal conditioning circuits may be used in front of the AD7701 without worrying about their absolute gain or offset errors ...
Page 14
... AGND Figure 18 shows the timing diagram for SSC mode. Data clocked out by an internally generated serial clock. The AD7701 SS SS divides each sampling interval into 16 distinct periods. Eight periods of 64 clock pulses are for analog settling and eight peri- 0.1µ ...
Page 15
... SCLK (I) HI-Z SDATA (O) REV. E SDATA goes three-state low and the AD7701 is still transmitting data when a new data-word becomes available, the old data-word continues to be transmitted and the new data is lost taken high at any time during data transmission, SDATA and SCLK will go three-state immediately returns low, the AD7701 will continue transmission with the same data bit ...
Page 16
... CMOS logic such as one of the 4000 series or 74C families is recommended especially important to minimize the load on SDATA in the AC mode, as transmission in this mode is inherently asynchro- nous. In the SEC mode, the AD7701 should be synchronized to the digital system clock via CLKIN. STOP STOP ...
Page 17
... Dimensions shown in millimeters 10.50 10.20 9.90 15 5.60 8.20 5.30 7.80 5.00 7.40 14 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.38 0.65 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AH (Q-20) Dimensions shown in inches and (millimeters) 0.098 (2.49) 0.005 (0.13) MAX 0.310 (7.87) MIN 0.220 (5.59 PIN 0.060 (1.52) 0.015 (0.38) 1.060 (26.92) MAX 0.150 (3.81) MIN SEATING 0.070 (1.78) 0.100 PLANE (2.54) 0.030 (0.76) BSC AD7701 8 0.95 4 0.75 0 0.55 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20 ...
Page 18
... AD7701 Revision History Location 3/03—Data Sheet changed from REV REV. E. Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 –18– Page REV. E ...
Page 19
–19– ...
Page 20
–20– ...