AD7709 Analog Devices, AD7709 Datasheet
AD7709
Specifications of AD7709
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AD7709 Summary of contents
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... The part operates from a single supply. When operating from 3 V supplies, the power dissipation for the part is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM REFIN1(+) REFIN2(+) IEXC2 ...
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... Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . 18 CONFIGURING THE AD7709 . . . . . . . . . . . . . . . . . . . . . 19 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MICROCOMPUTER/MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AD7709-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 21 AD7709-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 21 AD7709-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 21 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 22 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 23 Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 23 Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reference Input ...
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... Normal-Mode Rejection @ Common-Mode Rejection @ See Notes on page 5. REV 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 = to T MIN MAX AD7709A, AD7709B Unit 5.4 Hz min 105 Hz max 16 Bits min 13 Bits p-p 16 Bits p-p See Tables ± 30 ppm of FSR max ± ...
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... XTAL1 Only V , Input Low Voltage INL V , Input High Voltage INH V , Input Low Voltage INL V , Input High Voltage INH Input Currents (except XTAL) Input Capacitance AD7709A, AD7709B Unit mA nom 200 mA nom 25 ± typ 200 ppm/∞C typ ± 2.5 % max ± 2.5 % typ 20 ppm/∞C typ ± ...
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... AD7709 Test Conditions = 100 SOURCE = 100 SINK = 200 SOURCE 1 SINK Unipolar Mode ...
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... AD7709 TIMING CHARACTERISTICS Limit at T MIN Parameter (A, B Version) t 30.5176 Read Operation 100 6 t 100 100 10 Write Operation 100 ...
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... A WITH V SOURCE 100 A WITH V Figure 1. Load Circuit for Timing Characterization MSB Figure 2. Write Cycle Timing Diagram MSB Figure 3. Read Cycle Timing Diagram –7– AD7709 = 3V 3V LSB LSB ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD7709 in smaller batches of data. A weak pull- SCLK input. CS Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the 17 AD7709 in systems with more than one device on the serial bus frame synchronization signal in com- municating with the device ...
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... AD7709–Typical Performance Characteristics 32772 INPUT RANGE = 32771 UPDATE RATE = 19.79Hz 32770 32769 32768 32767 32766 32765 32764 0 100 200 300 400 500 600 READING NUMBER TPC 1. Typical Noise Plot on ± Input Range 3.0 2.56V RANGE 2.5 2 2.5V REF 1.5 INPUT RANGE = 2 ...
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... ADC CIRCUIT INFORMATION Overview The AD7709 incorporates a - ADC channel with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure transducer, or temperature measurement applications. - ADC This channel can be programmed to have one of eight input voltage ranges from ± ...
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... ADC Normal mode rejection is the major function of the digital filter on the AD7709. The normal mode 50 ± rejection with an SF word typically –100 dB. The 60 ± rejection with typically –100 dB. Simultaneous 50 Hz and 60 Hz rejection of better than achieved with 69. ...
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... Second, when the analog input is converted into the digital domain, quantization noise is added. The device noise low Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise Data Update ...
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... Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part ...
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... This bit is automatically cleared. SR1 STBY Standby Bit Indication. When this bit is set, the AD7709 is in power-down mode. This bit is cleared when the ADC is powered up. SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies, etc ...
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... AD7709 Configuration Register (A1 Power-On-Reset = 000007H) The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations for this register ...
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... AIN4 AINCOM 0 AIN1 AIN2 1 AIN3 AIN4 0 AINCOM AINCOM 1 AIN2 AIN2 –17– AD7709 Positive Analog Input Positive Analog Input Positive Analog Input Positive Analog Input Positive and Negative Analog Inputs Positive and Negative Analog Inputs None Positive and Negative Analog Inputs ...
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... AD7709 Table VII. Configuration Register Bit Designations (continued) Bit Bit Location Name Description CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit. Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a code of FFFFh ...
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... Communications Register. The AD7709 begins converting on power-up without the need to write to the registers. The default conditions are used, i.e., the AD7709 operates at a 19.79 Hz update rate that offers 50 Hz and 60 Hz rejection. Figure 10 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7709 ...
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... Figures 2 and 3 show timing diagrams for interfacing to the AD7709 with CS used to decode the part. Figure 3 is for a read operation from the AD7709 output shift register while Figure 2 shows a write operation to the input shift register possible to read the same data twice from the output register even though the RDY line returns high after the first read operation ...
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... RDY. The second scheme is to use an interrupt driven system, in which case the RDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7709, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input. ...
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... ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7709 is active when either the RFS or TFS outputs from the ADSP-2103/ ADSP-2105 are active. The serial clock rate on the ADSP-2103/ ADSP-2105 should be limited to 3 MHz to ensure correct opera- tion with the AD7709 ...
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... AIN(+) input AIN(–) is 2.5 V and the AD7709 is configured for an analog input range of ± 1.28 V, the analog input range on the AIN(+) input is 1. 3.78 V (i.e., 2.5 V ± 1.28 V). Bipolar or unipolar options are chosen by programming the UNI bit in the Configuration Register ...
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... The device power-down mode does not affect the digital interface, but it does affect the status of the RDY pin. Putting the AD7709 into power-down mode will reset the RDY line high. Placing the part in power-down mode reduces the total current typical when the part is operated with the oscillator running during power-down mode ...
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... The analog ground plane should be allowed to run under the AD7709 to prevent noise coupling. The power supply lines to the AD7709 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like ...
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... RL1 and RL4, but these simply shift the common-mode voltage. There is no voltage drop across lead resistances RL2 and RL3 XTAL1 since the input current to the AD7709 is very low, looking into a high input impedance buffer. R input voltage to ensure that it lies within the common-mode ...
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... The typical drift matching between the two RTD current sources is less than 20 ppm/∞C. The voltage on either I can go to within 0 the V The AD7709 also includes current source that can be used along with the two 200 mA current sources for V where a 17:1 ratio is required from the current sources. ...
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... AD7709 Smart Transmitters Smart transmitters are another key design-in area for the AD7709. The - converter, single-supply operation, 3-wire interface capabilities, and small package size are all of benefit in smart transmitters. Here, the entire smart transmitter must operate from the 4–20 mA loop. Tolerances in the loop mean that the ...
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... Thin Shrink Small Outline Package [TSSOP] PIN 1 0.15 0.05 REV. A OUTLINE DIMENSIONS (RU-24) Dimensions shown in millimeters 7.90 7.80 7. 4.50 4.40 4.30 6.40 BSC 1 12 0.65 1.20 BSC MAX 8 0.30 0 0.20 SEATING 0.19 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD –29– AD7709 0.75 0.60 0.45 ...
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... AD7709 Revision History Location 3/03—Data Sheet changed from REV REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to Communications Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Table VIII. Filter Register Bit Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 –30– Page REV. A ...
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