AD7825 Analog Devices, AD7825 Datasheet
AD7825
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AD7825 Summary of contents
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... EOC (end of conversion) signal goes high logic low at that point, the ADC is powered down. The AD7822 and AD7825 also have a separate power-down pin (see the Operating Modes section). The parallel interface is designed to allow easy interfacing to microprocessors and DSPs ...
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... Power-Up Times......................................................................... 14 Power vs. Throughput................................................................ 15 Operating Modes........................................................................ 15 Parallel Interface......................................................................... 17 Microprocessor Interfacing........................................................... 18 AD7822/AD7825/AD7829 to 8051 ......................................... 18 AD7822/AD7825/AD7829 to PIC16C6x/PIC16C7x................ 18 AD7822/AD7825/AD7829 to ADSP-21xx ............................. 18 Interfacing Multiplexer Address Inputs .................................. 18 AD7822 Standalone Operation ................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 25 Changes to Typical Connection Diagram Section........................7 Changes to Analog Input Section....................................................8 Changes to Analog Input Selection Section...................................9 Changes to Power-Up Times Section ...
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... V min 0.8 V max 2 V min 0.4 V max ±1 μA max 10 pF max Rev Page AD7822/AD7825/AD7829 Test Condition/Comment kHz MHz IN SAMPLE fa = 27.3 kHz 28.3 kHz kHz IN See Analog Input section Input voltage span = 2.5 V Default V = 1.25 V MID Input voltage span = 2 V ...
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... AD7822/AD7825/AD7829 Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Track-and-Hold Acquisition Time Conversion Time POWER SUPPLY REJECTION V ± 10% DD POWER REQUIREMENTS Normal Operation Power-Down Power Dissipation ...
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... Power-up time from rising edge of CONVST using external 2.5 V reference , quoted in the timing characteristics is the true bus relinquish time 10 200µ OUTPUT PIN C L 50pF 200µ Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev Page AD7822/AD7825/AD7829 = 5 V ± 10%, and time required for an output DD 2.1V ...
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... AD7822/AD7825/AD7829 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter V to AGND DGND DD Analog Input Voltage to AGND IN1 IN8 Reference Input Voltage to AGND V Input Voltage to AGND MID Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range ...
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... Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary if the ADC is sharing a common data bus with another device. PD Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and AD7825 in power-down mode. The ADCs power up when PD is brought logic high again. RD Logic Input Signal ...
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... A measure of the level of crosstalk between channels measured by applying a full-scale 20 kHz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The figure given is the worst case across all four or eight channels of the AD7825 and + + + ...
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... V − 1 LSB, after the AD7825/AD7829. It means that the user must wait for the duration of the track-and-hold acquisition time after a channel change/step input change to V conversion, to ensure that the part operates to specification. ...
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... AD7822/AD7825/ DD AD7829 power low current mode, that is, power-down mode, with the default logic level on the EOC pin on the AD7822 and AD7825 equal to a low. Ensure the CONVST line is not floating when V is applied, because this can put the DD AD7822/AD7825/AD7829 into an unknown state ...
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... A rising edge on the CONVST pin causes the AD7829 to fully power up, while a rising edge on the PD pin causes the AD7822 and AD7825 to fully power up. For applica- tions where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance (see the Power vs ...
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... V ± 2%. Analog Input Structure Figure 15 shows an equivalent circuit of the analog input structure of the AD7822/AD7825/AD7829. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never AD7822/ exceeds the supply rails by more than 200 mV ...
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... When returning IN1 selected is the IN Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825 The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7822/AD7825/AD7829 ideal for subsampling applications. When the AD7825 is converting a 10 MHz input signal at a sampling rate of 2 MSPS, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dBs, as shown in Figure 18 ...
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... DD CONVST Figure 20 shows how to power up the AD7822 or AD7825 when V is first connected or after the ADCs have been powered down, DD using the PD pin or the CONVST pin, with either the on-chip reference or an external reference. When the supplies are first connected or after the part has been powered down by the PD ...
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... EOC pulse. Mode 1 Operation (High Speed Sampling) When the AD7822/AD7825/AD7829 are operated in Mode 1, they are not powered down between conversions. This mode of operation allows high throughput rates to be achieved. ...
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... DB0 TO DB7 The ADC is powered up again on the rising edge of the CONVST signal. Superior power performance can be achieved in this mode of operation by powering up the AD7822/AD7825/ AD7829 only to carry out a conversion. The parallel interface of the AD7822/AD7825/AD7829 remains fully operational while the ADCs are powered down. A read may occur while the part is powered down, and, therefore, it does not necessarily need to be placed within the EOC pulse, as shown in Figure 25 ...
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... Figure 26 shows a timing diagram illustrating the operational sequence of the AD7822/AD7825/AD7829 parallel interface. The multiplexer address is latched into the AD7822/ AD7825/AD7829 on the falling edge of the RD input. The on- chip track-and-hold goes into hold mode on the falling edge of CONVST , and a conversion is also initiated at this point. When ...
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... ADDITIONAL PINS OMITTED FOR CLARITY. Figure 28. Interfacing to the PIC16C6x/ PIC16C7x AD7822/AD7825/AD7829 TO ADSP-21xx Figure 29 shows a parallel interface between the AD7822/ AD7825/AD7829 and the ADSP-21xx series of DSPs. As before, the EOC signal on the AD7822/AD7825/AD7829 provides an interrupt request to the DSP when a conversion ends. 1 ADSP-21xx ...
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... AD7822 can be selected AD7825/ RD AD7829 CS A15 DB7 TO DB0 DB0 TO DB7 Figure 30. AD7825/AD7829 Simplified Microinterfacing Scheme CONVST DSP/ LATCH/ASIC EOC CS RD DB0 TO DB7 Figure 31. AD7822 Standalone Operation Rev Page AD7822/AD7825/AD7829 MICROPROCESSOR READ CYCLE ADC I/O ADDRESS MUX ADDRESS ...
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... AD7822/AD7825/AD7829 OUTLINE DIMENSIONS PIN 1 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.060 (26.92) 1.030 (26.16) 0.980 (24.89 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 10 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.015 (0.38) MIN GAUGE PLANE SEATING PLANE 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AD CONTROLLING DIMENSIONS ARE IN INCHES ...
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... PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) Rev Page AD7822/AD7825/AD7829 4.50 4.40 4.30 6.40 BSC 0.20 0.09 0.75 8° ...
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... AD7822/AD7825/AD7829 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.15 0.05 15.60 (0.6142) 15.20 (0.5984 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) SEATING 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. ...
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... CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. 28-Lead Standard Small Outline Package [SOIC_W] Dimensions shown in millimeters and (inches) Rev Page AD7822/AD7825/AD7829 15 0.580 (14.73) 0.485 (12.31) 14 0.625 (15.88) 0.600 (15.24) ...
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... AD7822/AD7825/AD7829 PIN 1 0.15 0.05 COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 SEATING 0.19 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 40. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 ...
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... AD7825BRZ-REEL 1 −40°C to +85°C 1 AD7825BRZ-REEL7 −40°C to +85°C AD7825BRU −40°C to +85°C AD7825BRU-REEL −40°C to +85°C AD7825BRU-REEL7 −40°C to +85°C 1 AD7825BRUZ −40°C to +85°C 1 AD7825BRUZ-REEL −40°C to +85°C 1 AD7825BRUZ-REEL7 −40°C to +85°C AD7829BN − ...
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... AD7822/AD7825/AD7829 NOTES Rev Page ...
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... NOTES AD7822/AD7825/AD7829 Rev Page ...
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... AD7822/AD7825/AD7829 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01321-0-8/06(C) Rev Page ...