AD7834 Analog Devices, AD7834 Datasheet
AD7834
Specifications of AD7834
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AD7834 Summary of contents
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... V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming CLR is exercised). The AD7834 is available in a 28-lead 0.3" SOIC package and a 28-lead 0.6" PDIP package, and the AD7835 is available in a 44-lead MQFP package and a 44-lead PLCC package. ...
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... AD7834 to ADSP-2101 Interface ............................................. 20 AD7834 to DSP56000/DSP56001 Interface............................ 21 AD7834 to TMS32020/TMS320C25 Interface....................... 21 Interfacing the AD7835—16-Bit Interface.............................. 21 Interfacing the AD7835—8-Bit Interface................................ 22 Applications Information .............................................................. 23 Serial Interface to Multiple AD7834s ...................................... 23 Opto-Isolated Interface ............................................................. 23 Automated Test Equipment ...................................................... 23 Power Supply Bypassing and Grounding................................ 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 27 ...
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... DSG ±5% for specified performance. ±5% for specified performance. ±5% for specified performance DGND. INH CC INL AD7834 2.4 V min 0.8 V max. INH INL AD7835 2.4 V min 0.8 V max. INH INL AD7834: outputs unloaded. AD7835: outputs unloaded. Outputs unloaded. ...
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... DSG ±5% for specified performance. ±5% for specified performance. ±5% for specified performance DGND. INH CC INL AD7834 2.4 V min 0.8 V max. INH INL AD7835 2.4 V min 0.8 V max. INH INL AD7834: outputs unloaded. AD7835: outputs unloaded. Outputs unloaded. ...
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... These characteristics are included for design guidance and are not subject to production testing. Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse DC Output Impedance Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough—AD7834 Digital Feedthrough—AD7835 Output Noise Spectral Density at 1 kHz Unit (typ) Test Conditions/Comments μ ...
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... FSYNC MSB D23 D22 DIN LDAC (SIMULTANEOUS UPDATE LDAC (PER-CHANNEL UPDATE) Figure 3. AD7834 Timing Diagram = −11 −15.75 V; AGND = DGND = Unit MIN MAX ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ...
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... V DD Package Type PDIP SOIC MQFP PLCC − T )/θ ESD CAUTION Rev Page AD7834/AD7835 must not exceed V by more than IN4148 SD103C AD7834/ AD7835 Figure 5. Diode Protection θ Unit JA 75 °C/W 75 °C/W 95 °C/W 55 °C/W ...
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... PA3 CONNECT Figure 6. AD7834 PDIP and SOIC Pin Configuration Description Negative Analog Power Supply: −15 V ± −12 V ± 5%. Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin. ...
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... Level-Triggered Chip Select Input (Active Low). The device is selected when this input is low. Level-Triggered Write Input (Active Low). When active used in conjunction with CS to write data over the input databus. Logic Power Supply ± 5%. Digital Ground. Rev Page AD7834/AD7835 ...
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... AD7834/AD7835 Pin No. MQFP Pin No. PLCC Pin Mnemonic DB0 to DB13 32 38 DSGB 36 (+)B, V REF 38 44 AGND 42 (+)A, V REF Description Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high ...
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... V (+) (V) REF Figure 11. Typical INL vs. V (+), V REF (−) = −6 V REF Rev Page AD7834/AD7835 0.50 0.45 DAC 1 0.40 0.35 DAC 3 DAC 4 0.30 0.25 DAC 2 0.20 0.15 0.10 0.05 TEMP = 25°C ALL DACs FROM 1 DEVICE 0 0 2.5 5.0 V (+) (V) REF Figure 12. Typical INL vs. V (+), V (+) – V REF REF 0 ...
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... AD7834/AD7835 0.7 VERT = 100mV/DIV HORIZ = 1μs/DIV 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 Figure 15. Typical Digital/Analog Glitch Impulse 8 VERT = 2V/DIV HORIZ = 1.2μs/DIV (+) = +7V REF 2 V (–) = –3V REF 0 –2 VERT = 25mV/DIV HORIZ = 2.5μs/DIV –4 Figure 16. Settling Time(+) (+) = +7V REF 2 V (–) = –3V ...
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... Channel-to-channel isolation refers to the proportion of input signal from the reference input of one DAC that appears at the output of the other DAC expressed in decibels (dB). The AD7834 has no specification for channel-to-channel isolation because it has one reference for all DACs. Channel-to-channel isolation is specified for the AD7835. ...
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... DAC outputs until the LDAC signal is exercised. DATA LOADING—AD7834 SERIAL INPUT DEVICE A write operation transfers 24 bits of data to the AD7834. The first 8 bits are control data and the remaining 16 bits are DAC data (see Figure 18). The control data identifies the DAC chan- nel to be updated with new data and which of 32 possible packages the DAC resides in ...
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... SECOND MSB, DB12 MSB, DB13 SECOND LEADING ZERO FIRST LEADING ZERO Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834 gives the code table for unipolar operation of the AD7834/ AD7835. Offset and gain can be adjusted in Figure 19 as follows: • To adjust offset, disconnect the V ...
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... AD588 provides precision ±5 V tracking outputs that are fed to the V (+) and V (−) inputs of the AD7834/AD7835. REF REF The code table for bipolar operation of the AD7834/AD7835 is shown in Table 13. Table 13. Code Table for Bipolar Operation Binary Number in DAC Latch MSB LSB Analog Output (V ...
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... CONTROLLED POWER-ON OF THE OUTPUT STAGE A block diagram of the output stage of the AD7834/AD7835 is shown in Figure 21 capable of driving a load of 10 kΩ in parallel with 200 pF are transmission gates used control the power-on voltage present at V used in conjunction with the CLR input to set V defined voltage present at the DSG pin ...
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... DSG potential during power-on, the voltage applied to DSG should also be kept within the range AGND – AGND + 2 V. Once the AD7834/AD7835 have powered on and the on-chip amplifiers have settled, the situation is as shown in Figure 23. Any voltage subsequently applied to the DSG pin is buffered by ...
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... POWER-ON OF THE AD7834/AD7835 Power is normally applied to the AD7834/AD7835 in the following sequence: first V and V , then (+) and V (−). The V pins are not allowed to float when REF REF REF power is applied to the part. V (+) is not allowed to go below REF V (−) − 0 (−) is not allowed to go below V ...
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... MSB first. The AD7834 also expects the MSB of the 24-bit write first. Eight falling clock edges occur in the transmit cycle. To load data to the AD7834, PC7 is left low after the first eight bits are transferred. A second byte of data is then transmitted serially to the AD7834. Then, a third byte is transmitted and, when this transfer is complete, the PC7 line is taken high ...
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... Data can then be written to the AD7834 by writing three bytes to the serial port of the TMS32020/TMS320C25. In the configuration shown in Figure 30, the CLR input on the AD7834 is controlled by the XF output on the TMS32020/TMS320C25. The clock/timer circuit controls the LDAC input on the AD7834. Alternatively, LDAC can also be tied to ground to allow automatic update of the DAC latches after each transfer ...
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... AD7834/AD7835 INTERFACING THE AD7835—8-BIT INTERFACE Figure 32 shows an 8-bit interface between the AD7835 and a generic 8-bit microcontroller/DSP processor. Pin D13 to Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the processor are connected to Pin D7 to Pin D0 of the AD7835. ...
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... Figure 33 shows how the package address pins of the AD7834 are used to address multiple AD7834s. This figure shows only 10 devices, but AD7834s can each be assigned a unique address by hardwiring each of the package address pins DGND. Normal operation of the device occurs when is low ...
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... Digital and analog ground planes should be joined at only one place. If the AD7834/AD7835 are the only devices requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7834/ AD7835. If the +15V AD7834/AD7835 are in a system where multiple devices require 1 ...
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... PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev Page AD7834/AD7835 45° 8° 0° 1.27 (0.0500) 0.33 (0.0130) 0.40 (0.0157) 0.20 (0.0079) ...
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... AD7834/AD7835 0.048 (1.22) 0.042 (1.07) 6 0.048 (1.22) 7 PIN 1 0.042 (1.07) IDENTIFIER TOP VIEW (PINS DOWN 0.656 (16.66) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) 2.20 2.00 1.80 0.25 MIN 0.10 COPLANARITY VIEW A ROTATED 90° CCW 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.020 (0.51) 0.042 (1.07) MIN 40 39 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.032 (0.81) 0.026 (0.66 0.045 (1.14) 0.025 (0.64) 0.120 (3.05) SQ 0.090 (2.29) SQ COMPLIANT TO JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS ARE IN INCHES ...
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... AD7834BR-REEL −40°C to +85°C 1 AD7834BRZ −40°C to +85°C 1 AD7834BRZ-REEL −40°C to +85°C AD7834AN −40°C to +85°C AD7834ANZ 1 −40°C to +85°C AD7834BN −40°C to +85°C 1 AD7834BNZ −40°C to +85°C AD7835AP −40°C to +85°C AD7835AP-REEL − ...
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... AD7834/AD7835 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01006-0-8/07(D) Rev Page ...