AD7847 Analog Devices, AD7847 Datasheet
AD7847
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AD7847 Summary of contents
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... AD7837/AD7847–SPECIFICATIONS = + 100 pF [V REFA REFB L L Parameter A Version STATIC PERFORMANCE Resolution 12 ± Relative Accuracy ± Differential Nonlinearity 2 Zero Code Offset Error ± +25°C ± MIN MAX 2 Gain Error ± +25°C ± ...
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... AD7837BQ – 0 0.3 V AD7837SQ AD7847AN AD7847BN AD7847AR AD7847BR AD7847AQ AD7847BQ AD7847SQ NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. pin will float Plastic DIP Cerdip SOIC. AD7837/AD7847 5%, AGNDA = AGNDB = DGND = O V) Conditions/Comments Setup Time ...
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... DAC latches is not changed. For the AD7837 measured with LDAC held high. For the AD7847 measured with CSA and CSB held high. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code on the DAC latch of the other converter ...
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... AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin Mnemonic Description CSA 11 Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low. CSB 12 Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low. ...
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... AD7837/AD7847–Typical Performance Graphs 10 0 – +15V –15V +20Vp–p REF –20 DAC CODE = 111...111 – FREQUENCY – Hz 0.5 0 7.5V REF 0.3 0.2 INL 0.1 DNL 0 – Volts DD SS –50 – +15V –15V 20V p-p REF – ...
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... S8 SHOWN FOR ALL 1s ON DAC INTERFACE LOGIC INFORMATION—AD7847 The input control logic for the AD7847 is shown in Figure 11. The part contains a 12-bit latch for each DAC. It can be treated as two independent DACs, each with its own CS input and a com- mon WR input. CSA and WR control the loading of data to the DAC A latch, while CSB and WR control the loading of the DAC B latch ...
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... Similar connections apply for DAC B. When signal, the circuit performs 2-quad- IN rant multiplication. The code table for this circuit is shown in Table III. Note that on the AD7847 the feedback resistor R internally connected to V AD7837 AD7847 V REFA ...
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... BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 16 shows the AD7837/AD7847 connected for bipolar operation. The coding is offset binary as shown in Table IV. When signal, the circuit performs 4-quadrant multi- IN plication. To maintain the gain error specifications, resistors R1, R2 and R3 should be ratio matched to 0.01%. Note that on the ...
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... B B MICROPROCESSOR INTERFACING–AD7847 ≤ 4095) Figures show interfaces between the AD7847 and three A popular 16-bit microprocessor systems, the 8086, MC68000 and ≤ 4095) B the TMS320C10. In all interfaces, the AD7847 is memory- mapped with a separate memory address for each DAC latch. ...
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... AD0 ADDITIONAL PINS OMITTED FOR CLARITY AD7847–MC68000 Interface Figure 21 shows an interface between the AD7847 and the MC68000. Once again a single MOVE instruction loads the 12-bit word into the selected DAC latch. CSA and CSB are AND-gated to provide a DTACK signal when either DAC latch is selected ...
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... AD7837/AD7847 AD7837–6502/6809 Interface Figure 25 shows an interface between the AD7837 and the 6502 or 6809 microprocessor. For the 6502 microprocessor, the φ2 clock is used to generate the WR, while for the 6809 the E sig- nal is used. 24-Lead Plastic DIP (N-24) 1.228 (31.19) 1.226 (31.14 0.261 (6. PIN 1 0 ...