AD7859 Analog Devices, AD7859 Datasheet
AD7859
Specifications of AD7859
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AD7859 Summary of contents
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... The AD7859 is capable of 200 kHz throughput rate while the AD7859L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme ...
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... Output High Voltage 2.4 Output Low Voltage, V 0.4 OL Floating State Leakage Current 10 4 Floating-State Output Capacitance 10 Output Coding 1, 2 (AV , unless otherwise noted.) Specifications in () apply to the AD7859L. MAX Version Units Test Conditions/Comments 71 dB min Typically SNR (for L Version: f –78 dB max ...
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... The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) and the allowable system full-scale voltage applied between AIN(+) and AIN(– ...
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... The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice MHz for AD7859 and 1.8 MHz for AD7859L CLKIN ...
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... World Wide Web home page at http://www.analog.com. PINOUT FOR PLCC W/B 8 REF /REF 9 IN OUT AGND 11 AD7859 C 12 TOP VIEW REF1 (Not to Scale REF2 14 AIN0 15 AIN1 AIN2 16 17 AIN3 REV. A ABSOLUTE MAXIMUM RATINGS ...
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... Signal to (Noise + Distortion) = (6.02 N +1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7859/AD7859L defined as: THD (dB) 20 log where V is the rms amplitude of the fundamental and V ...
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... CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low, then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. ...
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... Addressing the On-Chip Registers Writing When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit word two 8-bit bytes, depending on the logic level at the W/B pin. When W/B is high, the 16 bits are transferred on DB0 to DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/B is low, DB8/HBEN assumes its HBEN functionality and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB ...
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... CHSLT1 CHSLT0 PMGT1 CONVST CALMD CALSLT1 (i.e., AIN(+) – AIN(– REF / REF REF . REF –9– AD7859/AD7859L PMGT0 RDSLT1 CALSLT0 STCAL LSB ). A logic 1 in REF /2 (i.e., AIN(+) – AIN(–) = – REF /2 to allow AIN(+) to have a full input REF ...
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... AIN5 AIN6 AIN7 AIN8 *AIN(+) refers to the positive input seen by the AD7859/AD7859L sample-and- hold circuitry. AIN(–) refers to the negative input seen by the AD7859/AD7859L sample-and- hold circuitry. CALMD CALSLT1 CALSLT0 ...
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... Start Calibration Bit. The STCAL bit calibration is in progress and there is no calibration in progress. REV. A START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER SGL/DIFF CHSLT2 CHSLT1 AMODE BUSY CALMD –11– AD7859/AD7859L CHSLT0 PMGT1 PMGT0 CALSLT1 CALSLT0 STCAL LSB ...
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... AD7859/AD7859L CALIBRATION REGISTERS The AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. ...
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... The maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage. –13– AD7859/AD7859L 13 )/2 volts. This equals 0.015 mV, with a 2 ...
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... CONVST rising edge. Reading/writing during conversion typically de- grades the Signal-to-(Noise + Distortion) by less than 0.5 dBs. The AD7859 can operate at throughput rates of over 200 kSPS (up to 100 kSPS for the AD7859L). With the AD7859L, 100 kSPS throughput can be obtained as follows: the CLKIN and CONVST signals are arranged to give a conversion time of 16 ...
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... In a single supply application (both 3 V and 5 V), the V+ and V– of the op amp can be taken directly from the supplies to the AD7859/AD7859L which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and out- puts at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for the application ...
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... V– AD820-3V 10k Figure 11. Analog Input Buffering Input Ranges The analog input range for the AD7859/AD7859L both the unipolar and bipolar ranges. REF The difference between the unipolar range and the bipolar range is that in the bipolar range the AIN(–) should be biased ...
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... C REF1 0.1µF C REF2 0.01µF REF 0.01µF Figure 17. Relevant Connections, AV REV. A AD7859/AD7859L PERFORMANCE CURVES Figure 18 shows a typical FFT plot for the AD7859 at 200 kHz sample rate and 10 kHz input frequency. /REF pin. These IN OUT pin and a 100 nF OUT 0.1µ Figure 19 shows the SNR versus Frequency for different sup- plies and different external references ...
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... The AD7859/AD7859L powers up from a full hardware or soft- ware power-down typ. This limits the throughput which the part is capable of to 100 kSPS for the AD7859 and 60 kSPS for the AD7859L when powering down between conversions. Figure 21 shows how power-down between conversions is implemented using the CONVST pin ...
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... The AD7859 TIME has a conversion time of 4.6 s with a 4 MHz external clock and the AD7859L has a conversion time with a 1.8 MHz clock. This means the AD7859/AD7859L consumes 4.5 mA/ 1.5 mA typ for 9.6 s/ every conversion cycle if the parts are powered down at the end of a conversion ...
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... AD7859 FULL POWER-DOWN CLKIN = 4MHz DD ON-CHIP REFERENCE 1 0.1 0. Figure 26. Power vs. Throughput AD7859 10 AD7859L FULL POWER-DOWN CLKIN = 1.8MHz DD ON-CHIP REFERENCE 1 0.1 0. Figure 27. Power vs. Throughput AD7859L –20– THROUGHPUT RATE – kSPS THROUGHPUT RATE – kSPS REV. A ...
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... STCAL bit to 1. The duration of each of the different types of calibration is given in Table IX for the AD7859 with a 4 MHz master clock. These calibration times are master clock dependent. Therefore the calibration times for the AD7859L (CLKIN = 1.8 MHz) are larger than those quoted in Table IX ...
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... Table IX. The timing diagram for the other self-calibration options is similar to that outlined in Figure 29. System Calibration Description System calibration allows the user to remove system errors ex- ternal to the AD7859/AD7859L, as well as remove the errors of the AD7859/AD7859L itself. The maximum calibration range for the system offset errors gain errors 2. ...
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... System Gain and Offset Interaction The architecture of the AD7859/AD7859L leads to an interac- tion between the system offset and gain errors when a system calibration is performed. Therefore recommended to per- form the cycle of a system offset calibration followed by a sys- tem gain calibration twice. When a system offset calibration is performed, the system offset error is reduced to zero ...
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... AD7859. When operated in word mode, the HBEN input does not exist, and only the first read operation is required to access data from the AD7859. Valid data, in this case, is pro- vided on DB0–DB15. When operated in byte mode, the two read cycles shown in Figure 36 are required to access the full data word from the AD7859 ...
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... AD7859. Data should be provided on DB0–DB15. When oper- ated in byte mode, the two write cycles shown in Figure 37 are required to write the full data word to the AD7859. In Figure 37, the first write transfers the lower 8 bits of the full data from DB0–DB7 and the second write transfers the upper 8 bits of the data word from DB0-DB7 ...
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... Figure 41 shows a parallel interface between the AD7859/ AD7859L and the DSP5600x series of DSPs. The AD7859/ AD7859L should be mapped into the top 64 locations of Y data memory. If extra wait states are needed in this interface, they can be programmed using the Port A Bus Control Register (please see DSP5600x Users Manual for details) ...
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... AD7859/AD7859L. REV. A The software allows the user to perform ac (fast Fourier trans- form) and dc (histogram of codes) tests on the AD7859/ AD7859L. It also gives full access to all the AD7859/AD7859L on-chip registers allowing for various calibration and power- down options to be programmed. AD785x Family All parts are 12 bits, 200 kSPS, 3 5.5 V. ...
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... PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 7 AD7859/AD7859L ON-CHIP REGISTERS . . . . . . . . . . . . . . . 8 Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . . . . 8 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 12 Addressing the Calibration Registers . . . . . . . . . . . . . . . . . . . 12 Writing to/Reading from the Calibration Registers . . . . . . . . 12 Adjusting the Offset Calibration Register . . . . . . . . . . . . . . . . 13 Adjusting the Gain Calibration Registers ...